PCE85133AUG All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 22 July 2015 23 of 50
NXP Semiconductors
PCE85133AUG
Universal 80 × 4 LCD driver for low multiplex rates
7. Characteristics of the I
2
C-bus
The I
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
By connecting pin SDAACK to pin SDA on the PCE85133AUG, the SDA line becomes
fully I
2
C-bus compatible. In COG applications where the track resistance from the
SDAACK pin to the system SDA line can be significant, possibly a voltage divider is
generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As
a consequence, it may be possible that the acknowledge generated by the
PCE85133AUG cannot be interpreted as logic 0 by the master. In COG applications
where the acknowledge cycle is required, it is therefore necessary to minimize the track
resistance from the SDAACK pin to the system SDA line to guarantee a valid LOW level.
By separating the acknowledge output from the serial data line (having the SDAACK open
circuit), design efforts to generate a valid acknowledge level can be avoided. However, in
that case the I
2
C-bus master has to be set up in such a way that it ignores the
acknowledge cycle.
2
The following definition assumes that SDA and SDAACK are connected and refers to the
pair as SDA.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as a control signal (see Figure 14
).
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START
condition (S).
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P).
2. For further information, consider the NXP application note: Ref. 1 “AN10170”.
Fig 14. Bit transfer
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