PCE85133AUG All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 22 July 2015 9 of 50
NXP Semiconductors
PCE85133AUG
Universal 80 × 4 LCD driver for low multiplex rates
When display data is transmitted to the PCE85133AUG, the received display bytes are
stored in the display RAM in accordance with the selected LCD drive mode. The data is
stored as it arrives and depending on the current multiplex drive mode the bits are stored
singularly, in pairs, triples or quadruples. To illustrate the filling order, an example of a
7-segment display showing all drive modes is given in Figure 4
; the RAM filling
organization depicted applies equally to other LCD types.
The following applies to Figure 4
:
• In static drive mode, the eight transmitted data bits are placed into row 0 as 1 byte.
• In 1:2 multiplex drive mode, the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words.
• In 1:3 multiplex drive mode, the 8 bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address, but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 6.3.2
).
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
6.3.1 Writing to RAM
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM.
The sequence always commences with the initialize-RAM command (see Table 6
).
Following this command, the data pointer has to be set to the desired RAM address using
the load-data-pointer command (see Table 7
). After this, an arriving data byte is stored at
the display RAM address indicated by the data pointer. The RAM writing procedure is
illustrated in Figure 5
and the filling order of the RAM is shown in Figure 4.
