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PCE85133AUG/DAZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
PCE85133AUG All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 22 July 2015 49 of 50
NXP Semiconductors
PCE85133AUG
Universal 80 × 4 LCD driver for low multiplex rates
24. Figures
Fig 1. Block diagram of PCE85133AUG . . . . . . . . . . . . .2
Fig 2. Pin configuration for PCE85133AUG. . . . . . . . . . .3
Fig 3. Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . . .7
Fig 4. Relationships between LCD layout, drive mode,
display RAM filling order, and display data
transmitted over the I
2
C-bus . . . . . . . . . . . . . . . . .8
Fig 5. RAM writing procedure . . . . . . . . . . . . . . . . . . . .10
Fig 6. Example of displays suitable for PCE85133AUG 13
Fig 7. Typical system configuration . . . . . . . . . . . . . . . .13
Fig 8. Electro-optical characteristic: relative
transmission curve of the liquid . . . . . . . . . . . . . .16
Fig 9. Static drive mode waveforms. . . . . . . . . . . . . . . .17
Fig 10. Waveforms for the 1:2 multiplex drive mode
with
1
⁄
2
bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Fig 11. Waveforms for the 1:2 multiplex drive mode
with
1
⁄
3
bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Fig 12. Waveforms for the 1:3 multiplex drive mode
with
1
⁄
3
bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Fig 13. Waveforms for the 1:4 multiplex drive mode
with
1
⁄
3
bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Fig 14. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Fig 15. Definition of START and STOP conditions. . . . . .24
Fig 16. System configuration . . . . . . . . . . . . . . . . . . . . . .24
Fig 17. Acknowledgement on the I
2
C-bus . . . . . . . . . . . .25
Fig 18. I
2
C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . .26
Fig 19. Control byte format . . . . . . . . . . . . . . . . . . . . . . .26
Fig 20. Device protection diagram . . . . . . . . . . . . . . . . . .27
Fig 21. Current consumption with respect to external
clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . .30
Fig 22. Frame frequency with respect to temperature . . .32
Fig 23. Driver timing waveforms . . . . . . . . . . . . . . . . . . .32
Fig 24. I
2
C-bus timing waveforms . . . . . . . . . . . . . . . . . .33
Fig 25. Schematic ITO connections when using the
internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . .33
Fig 26. Schematic ITO connections when using an
external oscillator. . . . . . . . . . . . . . . . . . . . . . . . .34
Fig 27. Bare die outline of PCE85133AUG . . . . . . . . . . .35
Fig 28. Alignment marks of PCE85133AUG . . . . . . . . . .39
Fig 29. Tray details of PCE85133AUG . . . . . . . . . . . . . .40
Fig 30. Die alignment in the tray . . . . . . . . . . . . . . . . . . .41
NXP Semiconductors
PCE85133AUG
Universal 80 × 4 LCD driver for low multiplex rates
© NXP Semiconductors N.V. 2015. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 July 2015
Document identifier: PCE85133AUG
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
25. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
6.1 Commands of PCE85133AUG. . . . . . . . . . . . . 5
6.2 Clock and frame frequency. . . . . . . . . . . . . . . . 6
6.2.1 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2.1.1 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2.1.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2.2 Frame frequency . . . . . . . . . . . . . . . . . . . . . . . 7
6.3 Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.3.1 Writing to RAM . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.3.2 RAM writing in 1:3 multiplex drive mode. . . . . 10
6.3.3 Writing over the RAM address boundary . . . . 11
6.3.4 Output bank selector . . . . . . . . . . . . . . . . . . . 11
6.3.5 Input bank selector . . . . . . . . . . . . . . . . . . . . . 12
6.4 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.5 Possible display configurations . . . . . . . . . . . 12
6.6 LCD bias generator . . . . . . . . . . . . . . . . . . . . 14
6.7 LCD voltage selector . . . . . . . . . . . . . . . . . . . 14
6.7.1 Electro-optical performance . . . . . . . . . . . . . . 15
6.8 LCD drive mode waveforms . . . . . . . . . . . . . . 17
6.8.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 17
6.8.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 18
6.8.3 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 20
6.8.4 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 21
6.9 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 22
6.10 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 22
7 Characteristics of the I
2
C-bus . . . . . . . . . . . . 23
7.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 START and STOP conditions . . . . . . . . . . . . . 23
7.3 System configuration . . . . . . . . . . . . . . . . . . . 24
7.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.5 I
2
C-bus controller . . . . . . . . . . . . . . . . . . . . . . 25
7.6 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.7 I
2
C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 25
8 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 27
9 Safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28
11 Static characteristics. . . . . . . . . . . . . . . . . . . . 29
12 Dynamic characteristics . . . . . . . . . . . . . . . . . 31
13 Application information . . . . . . . . . . . . . . . . . 33
14 Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 35
15 Handling information . . . . . . . . . . . . . . . . . . . 40
16 Packing information . . . . . . . . . . . . . . . . . . . . 40
16.1 Packing information on the tray . . . . . . . . . . . 40
17 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
17.1 LCD segment driver selection . . . . . . . . . . . . 42
18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44
19 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
20 Revision history . . . . . . . . . . . . . . . . . . . . . . . 45
21 Legal information . . . . . . . . . . . . . . . . . . . . . . 46
21.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 46
21.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
21.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 46
21.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 47
22 Contact information . . . . . . . . . . . . . . . . . . . . 47
23 Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
24 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
25 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

PCE85133AUG/DAZ

Mfr. #:
Buy PCE85133AUG/DAZ
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers Universal 80 × 4 LCD driver for low multiplex rates
Lifecycle:
New from this manufacturer.
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