PCE85133AUG All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 22 July 2015 6 of 50
NXP Semiconductors
PCE85133AUG
Universal 80 × 4 LCD driver for low multiplex rates
[1] The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes.
6.2 Clock and frame frequency
6.2.1 Oscillator
The internal logic and the LCD drive signals of the PCE85133AUG are timed by a
frequency f
clk
which either is derived from the built-in oscillator frequency f
osc
:
(1)
or equals an external clock frequency f
clk(ext)
:
(2)
6.2.1.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to V
SS
.
6.2.1.2 External clock
Connecting pin OSC to V
DD
enables an external clock source. Pin CLK then becomes the
external clock input.
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
Table 7. Load-data-pointer command bit description
See Section 6.3.1.
Bit Symbol Value Description
7 - 0 fixed value
6 to 0 P[6:0] 0000000 to
1001111
data pointer
7-bit binary value of 0 to 79, transferred to the
data pointer to define one of 80 display RAM
addresses
Table 8. Bank-select command bit description
[1]
See Section 6.3.4 and Section 6.3.5.
Bit Symbol Value Description
Static 1:2 multiplex
7 to 2 - 111110 fixed value
1I input bank selection: storage of arriving
display data
0 RAM row 0 RAM rows 0 and 1
1 RAM row 2 RAM rows 2 and 3
0O output bank selection: retrieval of LCD display
data
0 RAM row 0 RAM rows 0 and 1
1 RAM row 2 RAM rows 2 and 3
f
clk
f
osc
64
--------
=
