PCE85133AUG All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 22 July 2015 25 of 50
NXP Semiconductors
PCE85133AUG
Universal 80 × 4 LCD driver for low multiplex rates
7.5 I
2
C-bus controller
The PCE85133AUG acts as an I
2
C-bus slave receiver. It does not initiate I
2
C-bus
transfers or transmit data to an I
2
C-bus master receiver. The only data output from the
PCE85133AUG are the acknowledge signals from the selected devices. Device selection
depends on the I
2
C-bus slave address, on the transferred command data, and on the
hardware subaddress.
7.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.7 I
2
C-bus protocol
Two I
2
C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCE85133AUG. The entire I
2
C-bus slave address byte is shown in Table 13.
The PCE85133AUG is a write-only device and will not respond to a read access, therefore
bit 0 should always be logic 0. Bit 1 of the slave address byte that a PCE85133AUG will
respond to, is defined by the level tied to its SA0 input (V
SS
for logic 0 and V
DD
for logic 1).
The I
2
C-bus protocol is shown in Figure 18. The sequence is initiated with a START
condition (S) from the I
2
C-bus master which is followed by the PCE85133AUG slave
addresses.
Fig 17. Acknowledgement on the I
2
C-bus
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Table 13. I
2
C slave address byte
Slave address
Bit 7 6 5 4 3 2 1 0
MSB LSB
011100SA0R/W
