AD9940BCPZ Datasheet AD9940BSTZ, AD9940BCPZRL, AD9940BCPZ | P1-P3

High Speed, Correlated Double Sampler

with Integrated Timing Driver

AD9940

Rev. 0

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FEATURES

56 MSPS correlated double sampler (CDS) with 6 dB gain

On-chip horizontal and RG timing driver

Single-supply operation (2.7 V min )

Precision Timing™ core with 0.37 ns resolution at 56 MSPS

Low power CMOS: 105 mW at 2.7 V (115 mW at 3.0 V)

48-lead LQFP and 48-lead LFCSP packages

APPLICATIONS

Professional HDTV camcorders

Professional/high end digital cameras

Broadcast cameras

Industrial high speed cameras

High speed data-acquisition systems

GENERAL DESCRIPTION

The AD9940 is a high speed, correlated double sampler for

high speed digital imaging applications. Integrated with a

programmable timing driver using the Precision Timing

core, the AD9940 features a 56 MHz CDS amplifier with

6 dB of fixed gain, an internal voltage reference supply,

and timing control for all the high speed clocks necessary

for CCD imaging systems. The Precision Timing core allows

adjustment of high speed clocks with a resolution of 0.37 ns.

Output buffers are also included, providing drive strength for

PCB traces and direct connection to an image signal processor

such as the AD9941.

The AD9940 is ideal for applications that need to place the

CDS and VGA/ADC circuits on separate PC boards. The fully

differential outputs of the AD9940 provide good signal integ-

rity when interfaced with the differential input AD9941. The

AD9940 operates from a single 2.7 V power supply, typically

dissipates 105 mW (excluding the H/RG drive current), and is

packaged in 48-lead LQFP and 48-lead LFCSP packages.

FUNCTIONAL BLOCK DIAGRAM

DIFFN

CCDIN

REFT REFB

INTERNAL

REGISTERS

SYNC

GENERATOR

SDISCK

AD9940

PRECISION

TIMING

GENERATOR

REF

INTERNAL

CLOCKS

HORIZONTAL

DRIVERS

H1 TO H4

HD SHP

RST

05261-001

DIFFP

BUF

CDS

SHD

CLI

Figure 1.

AD9940

Rev. 0 | Page 2 of 20

TABLE OF CONTENTS

Specifications..................................................................................... 3

Analog Specifications................................................................... 4

Digital Specifications ................................................................... 5

Timing Specifications (Slave Timing Mode) ............................ 5

Absolute Maximum Ratings............................................................ 6

Thermal Characteristics .............................................................. 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Data Bit Descriptions ....................................................................... 9

Serial Interface Timing .................................................................. 12

System Overview ............................................................................ 13

Analog Front End Operation.................................................... 13

Precision Timing, High Speed Timing Generation................... 14

Timing Resolution...................................................................... 14

High Speed Clock Programmability........................................ 14

H-Driver and RG Outputs ........................................................ 16

HBLK Sequences ........................................................................ 17

Application Information................................................................ 19

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

7/05—Revision 0: Initial Version

AD9940

Rev. 0 | Page 3 of 20

SPECIFICATIONS

Table 1.

Parameter Min Typ Max Unit

TEMPERATURE RANGE

Operating −25 +85 °C

Storage −65 +150 °C

MAXIMUM CLOCK RATE 56 MHz

POWER SUPPLY VOLTAGE

AVDD, TCVDD (AFE, Timing Core) 2.7 3.0 3.6 V

OVDD (Analog Buffer) 2.7 3.0 3.6 V

DVDD (Digital) 2.7 3.0 3.6 V

HVDD (H1 to H4 Drivers) 2.7 3.0 3.6 V

RGVDD (RG Driver) 2.7 3.0 3.6 V

POWER DISSIPATION

56 MHz, AFE supplies = 2.7 V, HVDD = RGVDD = 3.2 V, 70 pF, H1 to H4 Loading 265 mW

56 MHz, AFE supplies = 3.0 V, HVDD = RGVDD = 3.2 V, 70 pF, H1 to H4 Loading 275 mW

56 MHz, AFE supplies = 2.7 V, no H or RG drivers 105 mW

56 MHz, AFE supplies = 3.0 V, no H or RG drivers 115 mW

Standby Mode 2 mW

The total power dissipated by the HVDD supply can be approximated using the following equation:

Total HVDD Power = (C

LOAD

× HVDD × Pixel Frequency) × HVDD

Reducing the H-loading and/or using a lower HVDD supply reduces the power dissipation.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

AD9940BCPZ

Mfr. #:

Buy AD9940BCPZ

Manufacturer:

Analog Devices Inc.

Description:

Data Acquisition ADCs/DACs - Specialized High Spd Correlated Double Sampler

Lifecycle:

New from this manufacturer.

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AD9940BCPZ

AD9940BCPZ

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