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AD9940BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
AD9940
Rev. 0 | Page 4 of 20
ANALOG SPECIFICATIONS
f
CLI
= 56 MHz, AVDD = OVDD = DVDD = TCVDD = 3.0 V, −25°C to +85°C, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Notes
CDS
Gain 5.0 5.5 6.0 dB
Allowable CCD Reset Transient
1
500 mV
Maximum Input Range Before Saturation
1
1 V p-p
Maximum CCD Black Pixel Amplitude
1
±50 mV
Peak Nonlinearity, 500 mV Input Signal 0.2 % FS
Power Supply Rejection (PSR) 36 dB Measured with step change on supply
ANALOG OUTPUTS
2
Typical DIFFP Output Signal Range 1.2 2.2 V 1.2 V corresponds to black level
Typical DIFFN Output Signal Range 1.2 2.2 V 2.2 V corresponds to black level
Typical Common Mode Level 1.7 V Midscale voltage where DIFFP = DIFFN
Maximum Differential Output Voltage Swing 2 V Defined as DIFFP − DIFFN
Output Voltage Compliance 1.0 2.4 V Limitation of output swing into external load
Maximum Load Capacitance 24 pF Value for each output (AD9941 C
IN
is < 24 pF)
Minimum Load Resistance (if required) 5,000 Ω
Only use resistive loading if required by the
differential receiver. Proper dc biasing should
be used to be compatible with levels in
Figure 3
1
Input signal characteristics are defined in Figure 2.
2
Output signal characteristics are defined in Figure 3.
50mV TYP
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
850mV TYP
INPUT SIGNAL RANGE
05261-002
Figure 2. Input Signal Characteristics
2.2V
1V MAX OUTPUT SIGNAL SWING, DIFFP AND DIFFN
2V p-p MAX DIFFERENTIAL SIGNAL, DIFFP–DIFFN
1.2V
DIFFP
GND
DIFFN
1.7V
BLACK
LEVEL
WHITE
LEVEL
05261-015
Figure 3. Output Signal Characteristics
AD9940
Rev. 0 | Page 5 of 20
DIGITAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = DVDD = OVDD = TCVDD = HVDD = RGVDD = 2.7 V, −25°C to +85°C, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V
IH
2.1 V
Low Level Input Voltage V
IL
0.6 V
High Level Input Current I
IH
10 μA
Low Level Input Current I
IL
10 μA
Input Capacitance C
IN
10 pF
LOGIC OUTPUTS
High Level Output Voltage, I
OH
= 2 mA V
OH
2.2 V
Low Level Output Voltage, I
OL
= 2 mA V
OL
0.5 V
CLI INPUT
High Level Input Voltage V
IH–CLI
1.85 V
Low Level Input Voltage V
IL–CLI
0.85 V
RG-DRIVER AND H-DRIVER OUTPUTS (powered by HVDD, RGVDD)
High Level Output Voltage (at max output current) V
OH
VDD − 0.5 V
Low Level Output Voltage (at max output current) V
OL
0.5 V
Maximum Output Current (programmable)
H-Driver (per output) 64 mA
RG-Driver, HL-Driver 15 mA
Maximum Load Capacitance
H-Driver (per output) 100 pF
RG-Driver, HL-Driver 50 pF
TIMING SPECIFICATIONS (SLAVE TIMING MODE)
See Figure 10 for Timing Diagram.
Table 4.
Parameter Symbol Min Typ Max Unit
MASTER CLOCK (CLI)
CLI Clock Period T
CLI
18 ns
CLI High Pulse Width T
ADC
9 ns
Internal Delay from CLI to First Tap T
CLIDLY
6 ns
SAMPLE CLOCKS
SHP Rising to SHD Rising T
S1
7.4 9 ns
ADCLK Edge Placement for AD9941 T
REC
3 ns
SERIAL INTERFACE
Maximum SCK Frequency f
SCLK
10 MHz
SL to SCK Setup Time t
LS
10 ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Rising Edge to SDATA Valid Hold t
DH
10 ns
AD9940
Rev. 0 | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter Rating
AVDD and TCVDD to AVSS −0.3 V to +3.9 V
−0.3 V to +3.9 V
HVDD and RGVDD to HVSS and
RGVSS
DVDD and OVDD to DVSS and OVSS −0.3 V to +3.9 V
Any VSS to Any VSS −0.3 V to +0.3 V
CLPOB/HBLK to DVSS −0.3 V to DVDD + 0.3 V
THERMAL CHARACTERISTICS
SCK, SL, and SDI to DVSS −0.3 V to DVDD + 0.3 V
RG to RGVSS −0.3 V to RGVDD + 0.3 V
θ
JA
is measured using a 4-layer PCB with the exposed paddle
soldered to the board.
H1–H4 to HVSS −0.3 V to HVDD + 0.3 V
REFT, REFB, and CCDIN to AVSS −0.3 V to AVDD + 0.3 V
Thermal resistance for 48-lead LQFP package:
Junction Temperature 150°C
θ
JA
= 92°C/W
Lead Temperature (10 sec) 350°C
Thermal resistance for 48-lead LFCSP package:
θ
JA
= 24°C/W
1
1
θ
JA
is measured using a 4-layer PCB with the exposed paddle
soldered to the board.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD9940BCPZ

Mfr. #:
Buy AD9940BCPZ
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized High Spd Correlated Double Sampler
Lifecycle:
New from this manufacturer.
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