AD9940BCPZ Datasheet AD9940BSTZ, AD9940BCPZRL, AD9940BCPZ | P10-P12

AD9940

Rev. 0 | Page 10 of 20

Address Data Bit Content Default Value Name Description

7 [0] 0 HBLKTOG1_1 [0] HBLKTOG1 position for Sequence 1 (Bit 0)

[1] 0 HBLKTOG1_1 [1] HBLKTOG1 position for Sequence 1 (Bit 1)

[2] 0 HBLKTOG1_1 [2] HBLKTOG1 position for Sequence 1 (Bit 2)

[3] 0 HBLKTOG1_1 [3] HBLKTOG1 position for Sequence 1 (Bit 3)

[4] 0 HBLKTOG1_1 [4] HBLKTOG1 position for Sequence 1 (Bit 4)

[5] 0 HBLKTOG1_1 [5] HBLKTOG1 position for Sequence 1 (Bit 5)

[6] 1 HBLKTOG1_1 [6] HBLKTOG1 position for Sequence 1 (Bit 6)

[7] 0 HBLKTOG1_1 [7] HBLKTOG1 position for Sequence 1 (Bit 7)

8 [0] 0 HBLKTOG2_1 [8] HBLKTOG2 position for Sequence 1 (Bit 8)

[1] 0 HBLKTOG2_1 [9] HBLKTOG2 position for Sequence 1 (Bit 9)

[2] 0 HBLKTOG2_1 [10] HBLKTOG2 position for Sequence 1 (Bit 10)

[3] 0 HBLKTOG2_1 [11] HBLKTOG2 position for Sequence 1 (Bit 11)

[7:4] 0 TESTMODE Always set = 0

9 [0] 0 HBLKTOG2_1 [0] HBLKTOG2 position for Sequence 1 (Bit 0)

[1] 0 HBLKTOG2_1 [1] HBLKTOG2 position for Sequence 1 (Bit 1)

[2] 0 HBLKTOG2_1 [2] HBLKTOG2 position for Sequence 1 (Bit 2)

[3] 0 HBLKTOG2_1 [3] HBLKTOG2 position for Sequence 1 (Bit 3)

[4] 0 HBLKTOG2_1 [4] HBLKTOG2 position for Sequence 1 (Bit 4)

[5] 0 HBLKTOG2_1 [5] HBLKTOG2 position for Sequence 1 (Bit 5)

[6] 1 HBLKTOG2_1 [6] HBLKTOG2 position for Sequence 1 (Bit 6)

[7] 0 HBLKTOG2_1 [7] HBLKTOG2 position for Sequence 1 (Bit 7)

10 [0] 0 HBLKTOG1_2 [8] HBLKTOG1 position for Sequence 2 (Bit 8)

[1] 0 HBLKTOG1_2 [9] HBLKTOG1 position for Sequence 2 (Bit 9)

[2] 0 HBLKTOG1_2 [10] HBLKTOG1 position for Sequence 2 (Bit 10)

[3] 0 HBLKTOG1_2 [11] HBLKTOG1 position for Sequence 2 (Bit 11)

[7:4] 0 TESTMODE Always set = 0

11 [0] 0 HBLKTOG1_2 [0] HBLKTOG1 position for Sequence 2 (Bit 0)

[1] 0 HBLKTOG1_2 [1] HBLKTOG1 position for Sequence 2 (Bit 1)

[2] 0 HBLKTOG1_2 [2] HBLKTOG1 position for Sequence 2 (Bit 2)

[3] 0 HBLKTOG1_2 [3] HBLKTOG1 position for Sequence 2 (Bit 3)

[4] 0 HBLKTOG1_2 [4] HBLKTOG1 position for Sequence 2 (Bit 4)

[5] 0 HBLKTOG1_2 [5] HBLKTOG1 position for Sequence 2 (Bit 5)

[6] 1 HBLKTOG1_2 [6] HBLKTOG1 position for Sequence 2 (Bit 6)

[7] 0 HBLKTOG1_2 [7] HBLKTOG1 position for Sequence 2 (Bit 7)

12 [0] 0 HBLKTOG2_2 [8] HBLKTOG2 position for Sequence 2 (Bit 8)

[1] 0 HBLKTOG2_2 [9] HBLKTOG2 position for Sequence 2 (Bit 9)

[2] 0 HBLKTOG2_2 [10] HBLKTOG2 position for Sequence 2 (Bit 10)

[3] 0 HBLKTOG2_2 [11] HBLKTOG2 position for Sequence 2 (Bit 11)

[7:4] 0 TESTMODE Always set = 0

13 [0] 0 HBLKTOG2_2 [0] HBLKTOG2 position for Sequence 2 (Bit 0)

[1] 0 HBLKTOG2_2 [1] HBLKTOG2 position for Sequence 2 (Bit 1)

[2] 0 HBLKTOG2_2 [2] HBLKTOG2 position for Sequence 2 (Bit 2)

[3] 0 HBLKTOG2_2 [3] HBLKTOG2 position for Sequence 2 (Bit 3)

[4] 0 HBLKTOG2_2 [4] HBLKTOG2 position for Sequence 2 (Bit 4)

[5] 0 HBLKTOG2_2 [5] HBLKTOG2 position for Sequence 2 (Bit 5)

[6] 1 HBLKTOG2_2 [6] HBLKTOG2 position for Sequence 2 (Bit 6)

[7] 0 HBLKTOG2_2 [7] HBLKTOG2 position for Sequence 2 (Bit 7)

AD9940

Rev. 0 | Page 11 of 20

Address Data Bit Content Default Value Name Description

14 [2:0] 3 RGDRV RG drive strength (resolution = 2.2 mA/Step):

0 = Off

1 = 2.2 mA

2 = 4.4 mA

…

7 = 15.4 mA

[3] 0 RGPOL

RG polarity:

0 = normal

1 = inverted

[6:4] 3 HLDRV HL drive strength (Resolution = 2.2 mA/Step):

0 = off

1 = 2.2 mA

2 = 4.4 mA

…

7 = 15.4 mA

[7] 0 HLPOL

HL polarity:

0 = normal

1 = inverted

15 [5:0] 0 HLPOSLOC HL rising edge location

[7:6] — Unused

16 [5:0] 24 HLNEGLOC HL negative edge location

[7:6] 0 Unused

17 [5:0] 0 RGPOSLOC RG rising edge location

[7:6] — Unused

18 [5:0] 24 RGNEGLOC RG negative edge location

[7:6] — Unused

19 [3:0] 7 H2/H4DRV H2/H4 drive strength (resolution = 4.3 mA/Step):

0 = Off

1 = 4.3 mA

2 = 8.6 mA

…

15 =64.5 mA

[7:4] 7 H1/H3DRV H1/H3 drive strength (resolution = 4.3 mA/Step):

0 = Off

1 = 4.3 mA

2 = 8.6 mA

…

15 = 64.5 mA

20 [5:0] 0 H1POSLOC H1 positive edge location

[6] — Unused

[7] 0 H1/H3POL H1/H3 polarity:

0 = normal

1 = inverted

(H2/H4 is opposite polarity of H1/H3)

21 [5:0] 32 H1NEGLOC H1 negative edge location

[7:6] — Unused

22 [5:0] 32 SHPLOC SHP sampling location

[7:6] 0 Unused

23 [5:0] 0 SHDLOC SHD sampling location

[7:6] — Unused

24 [7:0] 0 TESTMODE Always set = 0

25 [7:0] 0 TESTMODE Always set = 0

26 [7:0] 0 TESTMODE Always set = 0

AD9940

Rev. 0 | Page 12 of 20

SERIAL INTERFACE TIMING

All the internal registers of the AD9940 are accessed through

a 3-wire serial interface. Each register consists of an 8-bit data

byte starting with the LSB bit. As shown in

Every write operation must begin with a write to Address 0 to

specify Part select bit and Bank location, then followed with any

number of consecutive data words. Address 0 is always followed

by Address 01 or Address 14 depending on the value specified

for WRITEMODE (used for Bank selection).

Figure 5, the data

bits are clocked in on the rising edge of SCK after SL is asserted

low and the entire 8-bit word is latched in on the rising edge

of SL after the last MSB bit. Consecutive serial writes are per-

formed starting with Address 0 and ending with an address

MSB bit prior to asserting SL high.

A hard reset is recommended after power-up to reset the

AD9940 prior to performing a serial interface write. A hard

reset is performed by asserting the RST pin low for a mini-

mum of 10 μs. The serial interface pins SCK, SL, and SDI

must be in a know state after the RST has been applied.

The AD9940 contains two banks of registers, which are

programmed independently. Bank 1 consists of the registers

located at Address 0 to Address 13, and Bank 2 consists of

Address 14 to Address 26. The WRITEMODE register located

at Address 0 is used to select which register bank is written to.

SDAT

SCK

D3 D7

D3D2

D7 D0

...

ADDR 01

D3 D7 D0 D3

...

NOTES

1. ANY NUMBER OF ADJACENT REGISTERS CAN BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS 00.

2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED

FOR EACH REGISTER.

3. ALL LOADED REGISTERS ARE SIMULTANEOUSLY UPDATED ON THE RISING EDGE OF SL.

ADDR N ADDR N+1ADDR 00

05261-004

Figure 5. Serial Interface Operation

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

AD9940BCPZ

Mfr. #:

Buy AD9940BCPZ

Manufacturer:

Analog Devices Inc.

Description:

Data Acquisition ADCs/DACs - Specialized High Spd Correlated Double Sampler

Lifecycle:

New from this manufacturer.

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AD9940BCPZ

AD9940BCPZ

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