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AD9940BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
AD9940
Rev. 0 | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05261-003
48
AVSS
47
AVSS
46
NC
45
NC
44
NC
43
NC
42
NC
41
NC
40
REFT
39
REFB
38
AVSS
37
AVDD
35
CCDIN
34
AVSS
33
SHP
30
H1
31
AVSS
32
SHD
36
AVSS
29
H2
28
HVSS
27
HVDD
25
H4
26
H3
2
AVSS
3
AVDD
4
DIFFN
7
OVDD
6
OVSS
5
DIFFP
1
NC
8
TCVDD
9
CLI
10
TCVSS
12
DVDD
11
DVSS
NC = NO CONNECT
13
DVSS
14
SL
15
DVSS
16
SDI
17
SCK
18
RST
19
HD
20
NC
21
RG
22
HL
23
RGVSS
24
RGVDD
PIN 1
AD9940
TOP VIEW
(Not to Scale)
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Menumonic Type Description
1
1 NC NC No Connect. Connect to GND.
2 AVSS P Analog Ground.
3 AVDD P Analog Supply.
4 DIFFN AO CDS Output, Data (Negative).
5 DIFFP AO CDS Output, Data (Positive).
6 OVSS P Analog Output Buffer Ground.
7 OVDD P Analog Output Buffer Supply.
8 TCVDD P Analog Supply for Timing Core.
9 CLI DI Reference Clock Input.
10 TCVSS P Analog Ground for Timing Core.
11 DVSS P Digital Ground.
12 DVDD P Digital Logic Power Supply.
13 DVSS P Digital Ground.
14 SL DI 3-Wire Serial Load Pulse.
15 DVSS P Digital Ground.
16 SDI DI 3-Wire Serial Data Input.
17 SCK DI 3-Wire Serial Clock.
18 RST DI Hardware Reset (Low Active). Low = Reset state, High = Normal operation.
19 HD DI Horizontal Sync Pulse.
20 NC NC Do No Connect. Should be left floating.
21 RG DO CCD Reset Gate Clock.
22 HL DO HL Horizontal Clock.
23 RGVSS P RG Driver Ground.
24 RGVDD P RG Driver Power Supply.
25 H4 DO CCD Horizontal Clock 4.
26 H3 DO CCD Horizontal Clock 3.
27 HVDD P Horizontal Clock Driver Supply.
28 HVSS P Horizontal Clock Driver Ground.
29 H2 DO CCD Horizontal Clock 2.
30 H1 DO CCD Horizontal Clock 1.
31 AVSS P Analog Ground.
32 SHD DI Test Clock Input for CCD Data Phase Sampling.
AD9940
Rev. 0 | Page 8 of 20
Pin No. Menumonic Type
1
Description
33 SHP DI Test Clock Input for CCD Reset Phase Sampling.
34 AVSS P Analog Ground.
35 CCDIN AI CCD Signal Input.
36 AVSS P Analog Ground (CCD Signal Input Reference).
37 AVDD P Analog Supply.
38 AVSS P Analog Ground.
39 REFB AO Voltage Reference Bottom By-Pass. Decoupled to analog ground with a 0.1 μF capacitor.
40 REFT AO Voltage Reference Top By-Pass. Decoupled to analog ground with a 0.1 μF capacitor.
41 to 46 NC NC No Connect. Connect to GND.
47, 48 AVSS P Analog Ground.
1
Type: AI = analog input; AO = analog output; DI = digital input; DO = digital output; P = power.
AD9940
Rev. 0 | Page 9 of 20
DATA BIT DESCRIPTIONS
Table 7.
Address Data Bit Content Default Value Name Description
0 [0] 0 PARTSEL Part Select:
0 = select AD9940
1 = select AD9941
[1] 0 TESTMODE Always set = 0
[2] 0 SW RESET Reset registers:
1 = reset all registers to the default values
[3] 0 MODE 0 = slave mode
1 = master mode
[4] 0 STANDBY 0 = normal operation
1 = standby operation
[6:5] 0 TESTMODE Always Set = 0
[7] 0 WRITEMODE 0 = write to Address 1 to Address 13
1 = write to Address 14 to Address 26
1 [6:0] 0 TESTMODE Always set = 0
[7] 0 HBLKMASKPOL HBLK mask polarity:
0 = H1/H3 low, H2/H4 high
1 = H1/H3 high, H2/H4 low
2 [0] 0 HBLKTOG1_0 [8] HBLKTOG1 position for Sequence 0 (Bit 8)
[1] 0 HBLKTOG1_0 [9] HBLKTOG1 position for Sequence 0 (Bit 9)
[2] 0 HBLKTOG1_0 [10] HBLKTOG1 position for Sequence 0 (Bit 10)
[3] 0 HBLKTOG1_0 [11] HBLKTOG1 position for Sequence 0 (Bit 11)
[7:4] 0 TESTMODE Always set = 0
3 [0] 0 HBLKTOG1_0 [0] HBLKTOG1 position for Sequence 0 (Bit 0)
[1] 0 HBLKTOG1_0 [1] HBLKTOG1 position for Sequence 0 (Bit 1)
[2] 0 HBLKTOG1_0 [2] HBLKTOG1 position for Sequence 0 (Bit 2)
[3] 0 HBLKTOG1_0 [3] HBLKTOG1 position for Sequence 0 (Bit 3)
[4] 0 HBLKTOG1_0 [4] HBLKTOG1 position for Sequence 0 (Bit 4)
[5] 0 HBLKTOG1_0 [5] HBLKTOG1 position for Sequence 0 (Bit 5)
[6] 1 HBLKTOG1_0 [6] HBLKTOG1 position for Sequence 0 (Bit 6)
[7] 0 HBLKTOG1_0 [7] HBLKTOG1 position for Sequence 0 (Bit 7)
4 [0] 0 HBLKTOG2_0 [8] HBLKTOG2 position for Sequence 0 (Bit 8)
[1] 0 HBLKTOG2_0 [9] HBLKTOG2 position for Sequence 0 (Bit 9)
[2] 0 HBLKTOG2_0 [10] HBLKTOG2 position for Sequence 0 (Bit 10)
[3] 0 HBLKTOG2_0 [11] HBLKTOG2 position for Sequence 0 (Bit 11)
[7:4] 0 TESTMODE Always set = 0
5 [0] 0 HBLKTOG2_0 [0] HBLKTOG2 position for Sequence 0 (Bit 0)
[1] 0 HBLKTOG2_0 [1] HBLKTOG2 position for Sequence 0 (Bit 1)
[2] 0 HBLKTOG2_0 [2] HBLKTOG2 position for Sequence 0 (Bit 2)
[3] 0 HBLKTOG2_0 [3] HBLKTOG2 position for Sequence 0 (Bit 3)
[4] 0 HBLKTOG2_0 [4] HBLKTOG2 position for Sequence 0 (Bit 4)
[5] 0 HBLKTOG2_0 [5] HBLKTOG2 position for Sequence 0 (Bit 5)
[6] 1 HBLKTOG2_0 [6] HBLKTOG2 position for Sequence 0 (Bit 6)
[7] 0 HBLKTOG2_0 [7] HBLKTOG2 position for Sequence 0 (Bit 7)
6 [0] 0 HBLKTOG1_1 [8] HBLKTOG1 position for Sequence 1 (Bit 8)
[1] 0 HBLKTOG1_1 [9] HBLKTOG1 position for Sequence 1 (Bit 9)
[2] 0 HBLKTOG1_1 [10] HBLKTOG1 position for Sequence 1 (Bit 10)
[3] 0 HBLKTOG1_1 [11] HBLKTOG1 position for Sequence 1 (Bit 11)
[7:4] 0 TESTMODE Always set = 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD9940BCPZ

Mfr. #:
Buy AD9940BCPZ
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized High Spd Correlated Double Sampler
Lifecycle:
New from this manufacturer.
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