AD9940BCPZ Datasheet AD9940BSTZ, AD9940BCPZRL, AD9940BCPZ | P13-P15

AD9940

Rev. 0 | Page 13 of 20

SYSTEM OVERVIEW

ANALOG FRONT END OPERATION

Figure 6 shows the typical system block diagram for the

AD9940. The CCD output is processed by the AD9940’s

AFE circuitry, which consists of a correlated double sam-

pler (CDS) and output buffer. The differential output of the

AD9940 provides good signal integrity when interfaced with

the AD9941.

The AD9940 signal-processing chain is shown in Figure 7,

consisting of a dc restore circuit, CDS, and output buffer.

DC Restore

To reduce the large dc offset of the CCD output signal, a

dc restore circuit is used with an external 0.1 μF series

coupling capacitor. This restores the dc level of the CCD

signal to approximately 1.5 V to be compatible with the 3 V

analog supply of the AD9940.

To operate the AD9940, all CCD and AFE timing parameters

are programmed into the AD9940 from the system micro-

processor through the 3-wire serial interface. From the system

master clock, CLI, provided by the image processor or external

crystal, the AD9940 generates the CCD’s horizontal and reset

gate clocks and all internal AFE clocks.

Correlated Double Sampler

The CDS circuit samples each CCD pixel twice to extract

the video information and reject low frequency noise. The

timing diagram in

The H-drivers for H1 to H4, HL and RG, are included in the

AD9940, allowing these clocks to be directly connected to the

CCD. An H-drive voltage of up to 3.6 V is supported.

Figure 10 illustrates how the two internally

generated CDS clocks, SHP and SHD, are used to sample the

reference level and the data level, respectively, of the CCD

signal. The placement of the SHP and SHD sampling edges

is determined by the setting of the SHPLOC (Address 22)

and SHDLOC (Address 23) control registers. Placement of

these two clock edges is critical to achieve the best perform-

ance from the CCD.

CCD

H1–H4, HL, RG

AD9940

05261-005

OUT

BUFFER

0.1μF

CCDIN

BUF

OUT

DIFFN

DIFFP

DATA

TIMING

GENERATOR

AD9941

ADC

OUT

DATA

DIGITAL IMAGE

PROCESSING

ASIC

SERIAL

INTERFACE

DIGITAL

OUTPUTS

Figure 6. Typical System Block Diagram

DIFFN

CCDIN

REFT

REFB

AD9940

INTERNAL

REF

H1–H4, HL, RG

TIMING

GENERATION

05261-006

BUF

CDS

0.1μF

SHP

0.1μF

SHD

SHP SHD

PRECISION

TIMING

GENERATION

SERIAL INTERFACE

1.5V

DC RESTORE

DIFFP

Figure 7. AD9940 Signal-Processing Chain

AD9940

Rev. 0 | Page 14 of 20

PRECISION TIMING, HIGH SPEED TIMING GENERATION

HIGH SPEED CLOCK PROGRAMMABILITY

The AD9940 generates flexible, high speed timing signals

using the Precision Timing core. This core is the foundation for

generating the timing used for both the CCD and the AFE: the

reset gate RG, horizontal drivers H1 to H4, and the SHP/SHD

sample clocks. A unique architecture makes it routine for the

system designer to optimize image quality by providing precise

control over the horizontal CCD readout and the AFE corre-

lated double sampling.

Figure 9 shows how the high speed clocks, RG, HL, H1–H4, SHP,

and SHD are generated. The RG pulse has programmable rising

and falling edges, and can be inverted using the polarity control.

The horizontal clocks H1/H3 have programmable rising and

falling edges, and polarity control. The H2/H4 clocks are always

inverses of the H1/H3 H-driver outputs.

Table 8 summarizes the high speed timing registers and their

parameters. Each edge location setting is 6 bits wide, but only

48 valid edge locations are available. Therefore, the register

values are mapped into four quadrants, with each quadrant

containing 12 edge locations.

TIMING RESOLUTION

The Precision Timing core uses a 1× master clock input (CLI)

as a reference. This clock should be the same as the CCD pixel

clock frequency.

Figure 8 illustrates how the internal timing

core divides the master clock period into 48 steps or edge

positions. Therefore, the edge resolution of the Precision

Timing core is (t

CLI

/48).

Table 9 shows the correct reg-

ister values for the corresponding edge locations.

NOTES

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (

P[0] P[48] = P[0]P[12] P[24] P[36]

1 PIXEL

PERIOD

...

CLI

CLIDLY

POSITION

05261-007

CLIDLY

= 6 ns TYP).

Figure 8. High Speed Clock Resolution from CLI Master Clock Input

AD9940

Rev. 0 | Page 15 of 20

H2/H4

CCD SIGNA

PROGRAMMABLE CLOCK POSITIONS:

RG POLARITY.

RG RISING EDGE.

RG FALLING EDGE.

SHP SAMPLE LOCATION.

SHD SAMPLE LOCATION.

H1/H3 POLARITY.

H1/H3 RISING EDGE POSITION.

H1/H3 FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3).

HL POLARITY.

HL RISING EDGE.

HL FALLING EDGE.

05261-008

H1/H3

Figure 9. High Speed Clock Programmable Locations

N N+1 N+2 N+9 N+10

REC

SHPLOC

SHDLOC

ADCLK

(FOR AD9941)

DIFFP

DIFFN

CCD

SIGNAL

05261-009

VALID

Figure 10. SHP, SHD, and Data Output Timing

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

AD9940BCPZ

Mfr. #:

Buy AD9940BCPZ

Manufacturer:

Analog Devices Inc.

Description:

Data Acquisition ADCs/DACs - Specialized High Spd Correlated Double Sampler

Lifecycle:

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AD9940BCPZ

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