AD9940
Rev. 0 | Page 19 of 20
APPLICATIONS INFORMATION
All signals should be carefully routed on the PCB to main-
tain low noise performance. The CCD output signal should be
connected to the CCDIN pin through a 0.1 μF capacitor. The
CCD timing signals H1A/B to H2A/B and RG1 to RG2 should
be routed directly to the CCD with minimum trace lengths. The
clock inputs are located on the other side of the package, where
the analog pins are located, and should be connected to the
digital ASIC away from the analog and CCD clock signals.
All decoupling capacitors should be located as close as possible
to the package pins. Careful use of a split ground plane can be
effective to avoid the return current of horizontal driver flows
into analog ground, thereby reducing coupling noise.
Power-supply decoupling is very important for achieving low
noise performance.
Figure 15 shows the local high frequency
decoupling capacitors, but additional capacitance is recom-
mended for lower frequencies. Additional capacitors and
ferrite beads can further reduce noise.
A single ground plane is recommended for the AD9940. This
ground plane should be as continuous as possible, particularly
where analog pins are concentrated, to ensure that all analog
decoupling capacitors provide the lowest possible impedance
path between the power and bypass pins and their respective
ground pins.
When using the LFCSP package, it is recommended that the
exposed paddle on the bottom of the package be soldered
to a large pad, with multiple vias connecting the pad to the
ground plane.
05261-014
48
AVSS
47
AVSS
46
NC
45
NC
44
NC
43
NC
42
NC
41
NC
40
REFT
39
REFB
38
AVSS
37
AVDD
35
CCDIN
34
AVSS
33
SHP
30
H1
31
AVSS
32
SHD
36
AVSS
29
H2
28
HVSS
27
HVDD
25
H4
26
H3
2
AVSS
3
AVDD
4
DIFFN
7
OVDD
6
OVSS
5
DIFFP
1
NC
8
TCVDD
9
CLI
10
TCVSS
12
DVDD
11
DVSS
13
DVSS
14
SL
15
DVSS
16
SDI
17
SCK
18
RST
19
HD
20
NC
21
RG
22
HL
23
RGVSS
RGVDD
24
PIN 1
AD9940
TOP VIEW
(Not to Scale)
0.1μF
0.1μF
0.1μF
3V ANALOG SUPPY
0.1μF
0.1μF
DIFFN OUTPUT
DIFFP OUTPUT
3V ANALOG SUPPLY
3V ANALOG SUPPLY
3V ANALOG SUPPL
3V ANALOG SUPPLY
MASTER
CLOCK INPUT
4.7μF
0.1μF
+
0.1μF
3
SERIAL
INTERFACE
RST INPUT
HD INPUT
RG
HL
0.1μF
3V ANALOG SUPPLY
HORIZONTAL
CLOCKS TO CCD
4.7μF
0.1μF
+
2
CCD SAMPLING INPUTS
ANALOG OUTPUT
FROM CCD
3V ANALOG
SUPPLY
4
Figure 15. Recommended Circuit Configuration NC pin and supply name consistency
