®
Technology
SiI 164
PanelLink Transmitter
Data Sheet
Document # SiI-DS-0021-E.doc
SiI 164 PanelLink Transmitter
Data Sheet
SiI-DS-0021-E ii
Silicon Image, Inc.
SiI-DS-0021-E
June 2005
Application Information
To obtain the most updated Application Notes and other useful information for your design, please visit the Silicon
Image web site at www.siliconimage.com or contact your local Silicon Image sales office.
Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.
Trademark Acknowledgment
Silicon Image, the Silicon Image logo, PanelLink
®
and the PanelLink
®
Digital logo are registered trademarks of
Silicon Image, Inc. TMDS
TM
is a trademark of Silicon Image, Inc. VESA
®
, FPD
TM
are trademarks of the Video
Electronics Standards Association. I
2
C is a trademark of Philips Semiconductor. All other trademarks are the
property of their respective holders.
Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most recent data
sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.
Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.
Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.
All information contained herein is subject to change without notice.
Revision History
Revision Date Comment
SiI-DS-0021-A 01/99 Full Release
SiI-DS-0021-B 03/99 Internal Revision B release
SiI-DS-0021-C 04/02 New format. I
2
C programming and strapping mode
description,TFT mapping and Design Recommendations,
pin names ISEL/RST changed to ISEL/RST# and PD to
PD#.
SiI-DS-0021-D 09/02 Included Pb-free package. Added De-skew range.
Corrected PD# pin number.
SiI-DS-0021-E 06/05 Corrected D1 dimension. Corrected JEDEC code.
Included VCC details for power measurement. Added
Register Reset values and additional sample programming
code.
© 2005 Silicon Image, Inc.
SiI 164 PanelLink Transmitter
Data Sheet
iii SiI-DS-0021-E
TABLE OF CONTENTS
General Description........................................................................................................................................ 1
Features ...................................................................................................................................................... 1
SiI 164 Pin Diagram ....................................................................................................................................... 1
Functional Description .................................................................................................................................... 2
PanelLink TMDS Digital Core ..................................................................................................................... 2
I
2
C Interface and Registers......................................................................................................................... 2
Data Capture Logic ..................................................................................................................................... 3
Electrical Specifications .................................................................................................................................. 4
Absolute Maximum Conditions ................................................................................................................... 4
Normal Operating Conditions ..................................................................................................................... 4
Digital I/O Specifications ............................................................................................................................. 4
DC Specifications........................................................................................................................................ 5
AC Specifications ........................................................................................................................................ 6
Input Timing Diagrams ................................................................................................................................ 7
Pin Descriptions.............................................................................................................................................. 9
Input Pins .................................................................................................................................................... 9
Configuration Pins..................................................................................................................................... 10
Input Voltage Reference Pin ..................................................................................................................... 11
Power Management Pins.......................................................................................................................... 11
Differential Signal Data Pins ..................................................................................................................... 11
Reserved Pins........................................................................................................................................... 11
Power and Ground Pins............................................................................................................................ 11
I
2
C Registers................................................................................................................................................. 12
I
2
C Register Mapping................................................................................................................................ 12
I
2
C Register Definitions............................................................................................................................. 13
I
2
C Slave Interface and Address ............................................................................................................... 15
Data De-skew Feature .............................................................................................................................. 16
Data Latching Modes ................................................................................................................................ 17
I
2
C Programming Sequence ..................................................................................................................... 18
Enabling Hot Plug Detection Mode........................................................................................................... 18
Non-I
2
C/Strap Mode Configuration ........................................................................................................... 19
TFT Panel Data Mapping.............................................................................................................................. 21
Design Recommendations ........................................................................................................................... 24
1.5V to 3.3V I
2
C Bus Level-Shifting .......................................................................................................... 24
Voltage Ripple Regulation......................................................................................................................... 25
Decoupling Capacitors.............................................................................................................................. 26
Series Damping Resistors on Outputs...................................................................................................... 27
Differential Trace Routing ......................................................................................................................... 27
Package Dimensions and Marking Specification ......................................................................................... 29
Ordering Information..................................................................................................................................... 29

SII164CTG64

Mfr. #:
Manufacturer:
Lattice
Description:
1.65GBPS 12BIT INTERFACE TX GP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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