SiI 164 PanelLink Transmitter
Data Sheet
3 SiI-DS-0021-E
Data Capture Logic
Video data is input to the SiI 164 by way of a 12-bit or 24-bit interface. The functionality of this interface is affected
by several of the configuration register settings, as follows.
BSEL selects between 12-bit and 24-bit input bus widths.
DSEL selects between single-edge and dual-edge modes for the input clocks.
EDGE selects between rising and falling edge on the input clocks.
CLK+ and CLK- provide the one or two clocks required for latching the input data bus.
The PD# input selects the chip power down mode and allows for disabling of the TMDS outputs.
The ISEL/RST# input resets the HDCP engine and internal registers and is asserted after power up and receipt of
a stable input pixel clock.
SiI 164 PanelLink Transmitter
Data Sheet
SiI-DS-0021-E 4
Electrical Specifications
Absolute Maximum Conditions
Absolute Maximum Conditions are defined as the worst-case conditions the part will tolerate without sustaining
damage. Permanent device damage may occur if absolute maximum conditions are exceeded. Proper operation
under these conditions is not guaranteed. Functional operation should be restricted to the conditions described
under Normal Operating Conditions.
Symbol Parameter Min Typ Max Units
V
CC
Supply Voltage 3.3V -0.3 4.0 V
V
I
Input Voltage -0.3 V
CC
+ 0.3 V
V
O
Output Voltage -0.3 V
CC
+ 0.3 V
T
J
Junction Temperature (with power applied) 125
°C
T
STG
Storage Temperature -65 150
°C
Normal Operating Conditions
Symbol Parameter Min Typ Max Units
V
CC
Supply Voltage 3.0 3.3 3.6 V
V
CCN
Supply Voltage Noise 100 mV
P-P
T
A
Ambient Temperature (with power applied) 0 25 70
°C
θ
JA
Thermal Resistance (Junction to Ambient)
1
64
°C/W
θ
JC
Thermal Resistance (Junction to Case)
1
20
°C/W
Note
1. Airflow at 0m/s.
Digital I/O Specifications
Under normal operating conditions unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
V
IH
High Swing High-level Input
Voltage
V
REF =
V
CC
2.0 V
V
IL
High Swing Low-level Input
Voltage
V
REF =
V
CC
0.8 V
V
DDQ
2
Low Swing Voltage 1 3.0 V
V
SH
Low Swing High-level Input
Voltage
V
REF =
V
DDQ
/2 V
DDQ
/2 +
300mV
V
V
SL
Low Swing Low-level Input
Voltage
V
REF =
V
DDQ
/2 V
DDQ
/2 –
100mV
V
V
CINL
Input Clamp Voltage
1
I
CL
= -18mA GND -0.8 V
V
CIPL
Input Clamp Voltage
1
I
CL
= 18mA VCC + 0.8 V
I
IL
Input Leakage Current -10 10
µA
V
IH
High Swing High-level Input
Voltage
V
REF =
V
CC
2.0 V
Notes
1. Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions
2. VDDQ defines the maximum voltage level of Low Swing input. It is not an actual input voltage. Chip characterization for
Low Swing operation is performed at 1.5V only. Voltage level of Low Swing input should never exceed absolute
maximum rating.
SiI 164 PanelLink Transmitter
Data Sheet
5 SiI-DS-0021-E
DC Specifications
Under normal operating conditions unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
V
OD
Differential Voltage Single ended
peak to peak amplitude
R
LOAD
= 50, R
EXT_SWING
= 510
510 550 590 mV
V
DOH
Differential High-level Output AVCC V
Voltage
1
I
DOS
Differential Output Short Circuit
Current
1
V
OUT
= 0 V 5
µA
I
PD#
Power-down Current
2
0.2 1.0 mA
I
CCT
Transmitter Supply Current IDCK= 165 MHz, 1-pixel/clock
mode, R
EXT_SWING
= 510,
Worst Case Pattern
3
85
4
120
5
mA
Notes
1. Guaranteed by design.
2. Assumes all inputs to the transmitter are not toggling.
3. Black and white checkerboard pattern, each checker is one pixel wide.
4. Measurement taken at VCC = 3.30V.
5. Measurement taken at VCC = 3.60V.

SII164CTG64

Mfr. #:
Manufacturer:
Lattice
Description:
1.65GBPS 12BIT INTERFACE TX GP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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