SiI 164 PanelLink Transmitter
Data Sheet
SiI-DS-0021-E 16
Data De-skew Feature
The de-skew feature allows adjustment of the clock-to-data delay on the input of the SiI 164. When driven by a
chip with clock and data timings which do not meet the setup and hold time requirements of an SiI 164, the de-
skew register value can be modified to position the clock in the middle of the valid data time and meet the input
setup and hold times. As shown in Figure 12, changing the DK[3:1] value from 0b100 to 0b111 delays the internal
clock by approximately 750ps to 900ps, increasing setup time and reducing hold time. This is useful when the
input clock, IDCK, arrives too early.
The default values for DK[3:1] are shown in Table 1, along with approximate times per setting. Note that the
default is different when enabling I
2
C mode (ISEL/RST#=HIGH) versus non-I
2
C mode (ISEL/RST#=LOW).
Positive values of T
CD
move the clock later, increasing setup time. Negative values of T
CD
move the clock earlier,
increasing hold time.
Where:
T
CD
is the amount of setup/hold timing variation
DK[3:1] is the setting of the de-skew configuration pins or I
2
C registers
Table 1. Data De-Skew Estimated Values
DK[3:1]
De-Skew Time
T
CD
0b111
+0.75ns to +0.90ns
0b110
+0.50ns to +0.70ns
0b101
+0.20ns to +0.35ns
0b100
0 Default De-Skew
0b011
-0.20ns to -0.35ns
0b010
-0.50ns to –0.70ns
0b001
-0.75ns to –0.90ns
0b000
-1.0ns to -1.2ns
T
CD
CLK+
CLK-
DK[3:1]
0b000 0b100 0b111
D[23:0],
DE, VSYNC,
HSYNC,
CTL[3:1]
-
T
CD
default
Figure 12. SiI 164 Data De-skew Feature Timing
