SiI 164 PanelLink Transmitter
Data Sheet
21 SiI-DS-0021-E
TFT Panel Data Mapping
The following TFT data mapping tables are strictly listed for single link TFT applications only. SiI 143B, SiI 151B,
SiI 153B and SiI 161B all have the same pinout. As such mapping will be the same when SiI 143B or SiI 151B or
SiI 153B is used in place of SiI 161B.
Table 4. One Pixel/Clock Input/Output TFT Mode - VESA P&D and FPDI-2 Compliant
TFT VGA Output Tx Input Data Rx Output Data TFT Panel Input
24-bpp 18-bpp 160 164 161B 141B 24-bpp 18-bpp
B0 DIE0 D0 QE0 Q0 B0
B1 DIE1 D1 QE1 Q1 B1
B2 B0 DIE2 D2 QE2 Q2 B2 B0
B3 B1 DIE3 D3 QE3 Q3 B3 B1
B4 B2 DIE4 D4 QE4 Q4 B4 B2
B5 B3 DIE5 D5 QE5 Q5 B5 B3
B6 B4 DIE6 D6 QE6 Q6 B6 B4
B7 B5 DIE7 D7 QE7 Q7 B7 B5
G0 DIE8 D8 QE8 Q8 G0
G1 DIE9 D9 QE9 Q9 G1
G2 G0 DIE10 D10 QE10 Q10 G2 G0
G3 G1 DIE11 D11 QE11 Q11 G3 G1
G4 G2 DIE12 D12 QE12 Q12 G4 G2
G5 G3 DIE13 D13 QE13 Q13 G5 G3
G6 G4 DIE14 D14 QE14 Q14 G6 G4
G7 G5 DIE15 D15 QE15 Q15 G7 G5
R0 DIE16 D16 QE16 Q16 R0
R1 DIE17 D17 QE17 Q17 R1
R2 R0 DIE18 D18 QE18 Q18 R2 R0
R3 R1 DIE19 D19 QE19 Q19 R3 R1
R4 R2 DIE20 D20 QE20 Q20 R4 R2
R5 R3 DIE21 D21 QE21 Q21 R5 R3
R6 R4 DIE22 D22 QE22 Q22 R6 R4
R7 R5 DIE23 D23 QE23 Q23 R7 R5
Shift CLK Shift CLK IDCK IDCK ODCK ODCK Shift CLK Shift CLK
VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC
HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC
DE DE DE DE DE DE DE DE
For 18-bit mode, the Flat Panel Graphics Controller interfaces to the transmitter exactly the same as in the 24-bit
mode; however, 6 bits per channel (color) are used instead of 8. It is recommended that unused data bits be tied
low. As can be seen from the above table, the data mapping for less than 24-bit per pixel interfaces are MSB
justified. The data is sent during active display time while the control signals are sent during blank time. Note that
the three data channels (CH0, CH1, CH2) are mapped to Blue, Green and Red data respectively.
