SII164CTG64 Datasheet SII164CTG64 | P28-P30

SiI 164 PanelLink Transmitter

Data Sheet

SiI-DS-0021-E 24

Design Recommendations

1.5V to 3.3V I

C Bus Level-Shifting

To program the SiI 164 via I

C mode SDA and SCL swing level must be 3.3V. DVO sources have I

C swing of

1.5V. To ensure proper initialization of the SiI 164 a bi-directional voltage level-shifting circuit between the SiI 164

C bus and the VGA or driving source should be implemented. Two suggested components that can be used to

achieve this is by using either a dual N-channel transistor like Fairchild Semiconductor’s NDC7002N or the Philips

GTL2010 High Speed Bus Switch. Refer to Figure 16 for a schematic example using a dual N-channel transistor

for translating an I

C 1.5V signal to 3.3V I

C signal and vice versa.

1.5V

1.5V I

C DATA FROM VGA

2.2K

2.9V 3.3V

S D

2N7002

1.5V I

C CLK FROM VGA

3.3V2.9V

3.3V I

C CLK TO SiI 164

2.2K

3.3V I

C DATA TO SiI 164

S D

2N7002

Figure 16. I

C Bus Voltage Level-Shifting using Fairchild NDC7002N

Figure 17 illustrates a schematic example using the Philips GTL 2010 to achieve a 1.5V to 3.3V bi-directional

level-shift.

1.5V I

C DATA FROM VGA

3.3V I

C DATA TO SiI 164

2.2K

3.3V I

C CLK TO SiI 164

3.3V

200K

1.5V

1.5V I

C CLK FROM VGA

GTL2010

GND

SREF

GREF

DREF

D10

S10

Figure 17. I

C Bus Voltage Level Shifting using Philips GTL 2010

SiI 164 PanelLink Transmitter

Data Sheet

25 SiI-DS-0021-E

Voltage Ripple Regulation

The power supply to PVCC is very important to the proper operation of the Transmitter chips. PVCC does not

draw much current so any voltage regulator that can supply 50mA or more is sufficient. Two suggested voltage

regulators are TL431 from Texas Instruments or LM317 from National Semiconductor. Two examples are shown

in Figure 18 and Figure 19

(5V)

out

(3.3V) to PVCC1

and PVCC2

TL431

100-150 ohms

1K ohms

3K ohms

ref

Cathode

Anode

Ref

Figure 18. Voltage Regulation using TL431

Decoupling and bypass capacitors are also involved with power supply connections, as described in detail in

Figure 20 and Figure 21.

out

(3.3V) to PVCC1

and PVCC2

(5V)

240 ohms

390 ohms

OUT

ADJ

LM317EMP

Figure 19. Voltage Regulation using LM317

SiI 164 PanelLink Transmitter

Data Sheet

SiI-DS-0021-E 26

Decoupling Capacitors

Designers should include decoupling and bypass capacitors at each power pin in the layout. These are shown

schematically in Figure 21. Place these components as closely as possible to the SiI 164 pins, and avoid routing

through vias if possible, as shown in Figure 20, which is representative of the various types of power pins on the

transmitter.

VCC

Ferrite

Via to GND

VCC

GND

Figure 20. Decoupling and Bypass Capacitor Placement

VCCPIN

C1 C2

VCC

Figure 21. Decoupling and Bypass Schematic

The values shown in Table 7 are recommendations that should be adjusted according to the noise characteristics

of the specific board-level design. Pins in one group (such as VCC) may share C2, L1, and C3, each pin having

C1 placed as closely to the pin as possible.

Table 7. Recommended Components for Bypass and Decoupling Circuits

C1 C2 C3 L1

100 – 300 pF 2.2 – 10 µF 10 µF

200+ Ω

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SII164CTG64

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SII164CTG64