SII164CTG64 Datasheet SII164CTG64 | P4-P6

SiI 164 PanelLink Transmitter

Data Sheet

SiI-DS-0021-E iv

LIST OF TABLES

Table 1. Data De-Skew Estimated Values.................................................................................................... 16

Table 2. Sample Programming Sequence for SiI 164 in 12-bit Mode .......................................................... 18

Table 3. Non-I

C/Strap Mode Options .......................................................................................................... 20

Table 4. One Pixel/Clock Input/Output TFT Mode - VESA P&D and FPDI-2 Compliant.............................. 21

Table 5. 24-bit One Pixel/Clock Input with 24-bit Two Pixels/Clock Output TFT Mode................................ 22

Table 6. 18-bit One Pixel/Clock Input with 18-bit Two Pixels/Clock Output TFT Mode................................ 23

Table 7. Recommended Components for Bypass and Decoupling Circuits................................................. 26

LIST OF FIGURES

Figure 1. Pin Diagram for SiI 164 ................................................................................................................... 1

Figure 2. Functional Block Diagram ............................................................................................................... 2

Figure 3. Clock Cycle High/Low Times........................................................................................................... 7

Figure 4. Low Swing Differential Times .......................................................................................................... 7

Figure 5. ISEL/RST# Minimum Timing ........................................................................................................... 7

Figure 6. Input Data Setup/Hold Time to IDCK .............................................................................................. 8

Figure 7. VSYNC, HSYNC and CTL[3:1] Delay Time from DE ...................................................................... 8

Figure 8. DE High and Low Times.................................................................................................................. 8

Figure 9. I

C Data Valid Delay (driving Read Cycle data) .............................................................................. 8

Figure 10. I

C Byte Read.............................................................................................................................. 15

Figure 11. I

C Byte Write .............................................................................................................................. 15

Figure 12. SiI 164 Data De-skew Feature Timing ........................................................................................ 16

Figure 13. 12-bit Input Data Latching ........................................................................................................... 17

Figure 14. 24-bit Input Data Latching ........................................................................................................... 17

Figure 15. Non- I

C/Strap Mode Schematic Example .................................................................................. 19

Figure 16. I

C Bus Voltage Level-Shifting using Fairchild NDC7002N ........................................................ 24

Figure 17. I

C Bus Voltage Level Shifting using Philips GTL 2010 .............................................................. 24

Figure 18. Voltage Regulation using TL431 ................................................................................................. 25

Figure 19. Voltage Regulation using LM317 ................................................................................................ 25

Figure 20. Decoupling and Bypass Capacitor Placement............................................................................26

Figure 21. Decoupling and Bypass Schematic............................................................................................. 26

Figure 22. Series Input Damping Resistors for Driving Source ................................................................... 27

Figure 23. Example of Incorrect Differential Signal Routing ........................................................................ 27

Figure 24. Example of Correct Differential Signal Routing........................................................................... 28

Figure 25. Differential Trace Routing to DVI Connector(Top Side View) ..................................................... 28

Figure 26. 64-pin TQFP Package Dimensions (JEDEC code MS-026ACD) ............................................... 29

SiI 164 PanelLink Transmitter September 2002

Data Sheet

1 SiI-DS-0021-E

General Description

The SiI 164 transmitter uses PanelLink

Digital

technology to support displays ranging from VGA to

UXGA resolutions (25 - 165Mpps) in a single link

interface.

The SiI 164 transmitter has a highly flexible interface

with either a 12-bit mode (½ pixel per clock edge) or

24-bit mode 1 pixel per clock edge input for true color

(16.7 million) support. In 24-bit mode, the SiI 164

supports single or dual edge clocking. In 12-bit mode,

the SiI164 supports dual edge single clocking or

single edge dual clocking. The SiI 164 can be

programmed though an I

C interface. In addition the

SiI 164 also supports Receiver and Hot Plug

Detection.

PanelLink Digital technology simplifies PC design by

resolving many of the system level issues associated

with high-speed mixed signal design, providing the

system designer with a digital interface solution that

is quicker to market and lower in cost.

Features

• Scaleable Bandwidth: 25 - 165MHz Flexible

• Graphics Controller Interface: 12-bit or 24-bit

mode 1 pixel/clock inputs

• Flexible Input Clocking: Single clock single

edge (24-bit), Single clock dual edge (12-/24-

bit), Dual clock single edge (12-bit)

• I

C Slave Programming Interface up to 100kHz

• Low Voltage Interface: 3.3V with option for 1.0

to 3.0V Low Voltage Signal Mode

• Monitor Detection supported through hot plug

and receiver detection

• De-skewing Option varies input clock to input

data timing

• Low Power: 3.3V operation (120mA max.) and

Power Down mode (1mA max.)

• Cable Distance Support: over 5m with twisted

pair and fiber-optics ready

• Compliant with DVI 1.0 (DVI is backwards

compliant with VESA

P&D

and DFP)

• Standard and Pb-free packages (see pg 29)

SiI 164 Pin Diagram

VCC

VREF

HSYNC

VSYNC

CTL3/A3/DK3

CTL2/A2/DK2

CTL1/A1/DK1

EDGE/HTPLG

PD#

MSEN

VCC

ISEL/RST#

DSEL/SDA

BSEL/SCL

GND

PGND

PVCC1

EXT_SWING

AGND

TXC-

TXC+

AVCC

TX0-

TX0+

AGND

TX1-

TX1+

AVCC

TX2-

TX2+

VCC

RESERVED

DKEN

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

GND

PVCC2

D11

D10

IDCK-

IDCK+

GND

SiI

164

64-Pin TQFP

(Top View)

AGND

Figure 1. Pin Diagram for SiI 164

SiI 164 PanelLink Transmitter

Data Sheet

SiI-DS-0021-E 2

Functional Description

The SiI 164 is a DVI 1.0 compliant PanelLink transmitter in a compact package. It provides 24-bit data Input to

allow for panel support up to UXGA resolution. Figure 2 shows the functional blocks of the chip.

Registers

Configuration

Logic Block

SCL

SDA

EDGE/HTPLG

BSEL/SCL

DSEL/SDA

CTL/A/DK[3:1]

Slave

Machine

Data Capture

Logic Block

D[23:0]

IDCK+

IDCK-

VSYNC

HSYNC

TXC+

TX0+

TX1+

TX2+

VREF

MSEN

PanelLink

Digital

core

ISEL/RST

EXT_SWIN

DKEN

A[3:1]

Figure 2. Functional Block Diagram

PanelLink TMDS Digital Core

The PanelLink TMDS core encodes video information onto three TMDS differential data lines and the differential

clock. The video data is input by the Data Capture Logic Block, as a 12- or 24-bit bus, using one or two clocks

with one or two edges per clock. An attached monitor may be sensed using the HTPLG pin or internally with

Receiver Sense. This detected state may be output onto the MSEN pin. The device may be powered down using

the PD# pin or with an internal register. The SiI 164 is reset using the ISEL/RST# pin. A resistor tied to the

EXT_SWING pin is used to control the TMDS swing amplitude.

C Interface and Registers

The SiI 164 uses a slave I

C interface, capable of running at 100kHz. The slave I

C interface is not 5V tolerant. If

the switching levels from the host are not 3.3V, then a voltage level shifter must be used. See Figure 16 and

Figure 17 on page 24 for a system diagram.

A connected display may be detected using the DVI Hot Plug signal, attached to the HTPLG pin; or with the

Receiver Sense logic internal to the SiI 164. The state of the detection, or an interrupt signal indicating a change

of state, may be sent to the MSEN pin. This is useful to the host controller monitoring the SiI 164.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P34

SII164CTG64

Mfr. #:

Buy SII164CTG64

Manufacturer:

Lattice

Description:

1.65GBPS 12BIT INTERFACE TX GP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

SII164CTG64