Dual Channel Precision Universal Clock Generator and NCO
Data Sheet 12
Table 3 - Output modes
Each output is by default enabled or disabled by a logical AND of the OEn hardware pin value accessible in register 0x2 and one SPI
bit. The logical behavior of all relevant bits are shown in Figure 7.
Figure 7 - Output Enable/Disable
3.2.1 Output Control Pins
The outputs are controlled by either a hardware OE pin or a OE register based on the value in the override bit in the register. The
default values of the override bits are zeros, so the hardware pins control the outputs. When the hardware pin is enabled, the OEn
SPI bit is read-only showing the current state of the related hardware pin.
The OE1, OE2, OE3 and OE4 pins have 75 k pull-up resistors, while the OERef pin has a 50 k pull-down resistor.
To disable the hardware pin control, the associated override bit can be set in SPI register 0x2. When the ‘override’ bit is set to ‘1’, the
external OE pin is ignored, and its value is no longer passed into register 0x2. Instead the value of the OEn bit in register 0x2 is used
in its place, and can be set through the SPI. Under this configuration, both the override bit and OEn bit in register 0x2 must be set to
‘1’ to enable the output.
When an output changes from disabled to enabled, there is an approximately 2 microsecond delay before it begins switching. During
this delay, the outputs will settle to the appropriate DC levels according to the configured mode. After this initial delay, the outputs will
begin switching with precise periods and no ‘runt’ pulses.
When an output changes from enabled to disabled, it will stop switching at the appropriate DC levels according to the configured
mode. After it has stopped, the biases will be disabled and the output will be set to high impedance.
3.2.2 Output Electrical Format - (LVCMOS, LVDS, LVPECL, or HCSL)
The output format (mode) may be factory programmed and the output will operate in that mode at every power-up. In addition, the
mode may be changed by writing the new value into register 0x4 via the SPI. Although all five output buffers are independent, the
enables and modes may be programmed simultaneously.
Note that all of the output modes are differential except the LVCMOS mode. When LVCMOS is selected, the positive output pin has
the LVCMOS signal, and the negative (inverting) output pin is high impedance. In LVCMOS mode, the output should be series
terminated, or unterminated. Series termination consists of a 33 ohm resistor placed within 0.25 inches of the ZL30240 package. A
50 ohm transmission line driven with such a series termination will have reflections absorbed.
3.3 Reference Input
Two input references are available for the PLLs; a crystal oscillator which accepts standard crystals from 22 MHz to 54 MHz, and an
external reference that may be supplied as a differential or single ended signal, and optionally, prescaled. Either reference may be
utilized by either PLL through the internal selectors. Likewise, either reference may be selected for an optional output buffer that
supports LVCMOS, LVDS, LVPECL or HCSL. Each PLL can select its input independently.
Register 0x2 contains the reference select control bits. Register 0x3 contains the configuration bits for the input reference buffer,
prescaler, and reference output.
Three device pins are associated with the input signal: In_p, In_n and In_VCM. For differential signals, In_p and In_n are the signal
and In_VCM is the terminating voltage. A LVCMOS single ended signal needs to be applied to In_p only. The input signal then goes
through a reference divider.
11 HCSL
OEn_override
VDD for OE[1:4]
0
1
SPI OEn
PU1_b
VSS for OEref
OEn pin
or SPI for PLL2
