Dual Channel Precision Universal Clock Generator and NCO
Data Sheet 16
7. The SPI master initiates a data transfer by dropping CSB to enable the slave device, followed by eight bits of data
applied synchronously with eight pulses of SCK. The first four bits define the opcode, and the last four bits define
the register to be addressed. The data stream is shown in the following diagram:
Figure 8 - Example SPI Read
The register addresses ADDR[3:0] define an address space for up to 16 registers. The following four opcodes are defined by the
interface:
The default state for CSB high is opcode zero, or no-op. The “read” opcodes are followed by one or more series of eight SCK pulses.
Data from the register addressed by ADDR are placed on SDO, msb first. The number of eight-pulse cycles is determined by the
type of register defined at address ADDR. The “write” opcodes are followed by one or more series of eight SCK pulses, with data to
be written to the addressed register placed on SDI and valid at the rising edge of SCK.
The core circuits of the chip see the new contents of each byte on the falling edge of the eighth SCK pulse, with the exception of
registers 6 and 8, all bits of which are updated simultaneously on the falling edge of the eighth SCK pulse of the last (5th) byte.
Figure 9 - Read (opcode 2) cycle
OP[3:0] Operation
0000 no-op
0001 write data
0010 read data
0011 reserved
Table 7 - SPI Operation Codes
OP[3] OP[2] OP[1] OP[0] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
CSB
SCK
SDI
SDO
SDO output is defined to be zero during the command and address input cycles
data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0]
SDO data valid
any data on SDI are ignored
CSB
SCK
SDI
SDO
CSB must be held low through the entire operation
