Dual Channel Precision Universal Clock Generator and NCO
Data Sheet 24
7:0 output1_div[7:0] Output divider 1 can be set to 4 to 259
For values 4 to 255, the output divider is set to the value of bits 7:0.
For values 0 to 3:
Value output1_div
0256
1257
2258
3259
For the output4_div = 4.5, see register 3, Device_config2, bit 8.
Register_Address: 0x6
Register Name: PLL1_config1
Default Value: 0x000000000E
Type: R/W
Bit Field Function Name Description
39:4 divval[35:0] Feedback Divider Value
If rational1 = 0, the divider value for PLL1 uses bits [40:5] for the
feedback divider. The top 8 bits represent the integer part and the bottom
28 bits represent the fixed-point part of the divider.
if rational = 1, then the S (see Register 7) controls the interpretation of
the feedback value:
If S=0, fbdiv = A + (1/8)(B+C/D) where A is in divval[35:28], B is in
divval[27:25], C is in divval [24:9] and D is in modulus[15:0].
If S=1, fbdiv = A + (1/4)(B+C/D) where A is in divval[35:28], B is in
divval[27:26], C is in divval [24:9] and D is in modulus[15:0].
If S=2, fbdiv = A + (1/2)(B+C/D) where A is in divval[35:28], B is in
divval[27], C is in divval[24:9] and D is in modulus[15:0].
If S=3, fbdiv = A + C/D where A is in divval[35:28], C is in divval[24:9]
and D is in modulus[15:0]. (B is ignored.)
Note: Modulus [15:6] is found in register 0x7, bits 9:0 and Modulus [5:0] is in
divval[5:0] when using rational mode.
3:0 Reserved Leave as default
Register_Address: 0x5
Register Name: Output_divider
Default Value: 0x00000000
Type: R/W
Bit Field Function Name Description