Dual Channel Precision Universal Clock Generator and NCO
Data Sheet 26
15 advance1 This bit, one for each PLL, is an active control that shifts the output of the
VCO forward one of eight phases (1/8 cycle). This phase shift happens
regardless of the setting S for the PLL. The phase advance is edge-
triggered, so no further phase advancement will occur until the bit is set
back to zero and raised again. This feature can be used to precisely
align the phases of the two PLLs.
14 fbdiv_reset1 Toggle this bit to 1 after a change in M1, S1 or divval1
13 output1_2_reset Toggle this bit to 1 to reset the outputs on PLL1 after a change in
output1_div or output2_div
12 force_reset1 Toggle this bit to 1 to reset PLL1
This signal forces a reset cycle that generates synchronization pulses for
the outputs of PLL1.
11 decline1 This bit, one for each PLL, is an active control that shifts the output of the
VCO backward one of eight phases (1/8 cycle).
See bit 15 for more information.
10 rational_mode1 See description for PLL1_configure_1 bits 39:4
9:0 modulus1[15:6] See description for PLL1_configure_1 bits 39:4
Register_Address: 0x8
Register Name: PLL2_config1
Default Value: 0x000000000E
Type: R/W
Bit Field Function Name Description
39:4 divval2[35:0] See description for PLL1_configure_1 (0x06)
3:0 Reserved Leave as default
Register_Address: 0x7
Register Name: PLL1_config2
Default Value: 0x0000000000
Type: R/W
Bit Field Function Name Description
