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ZL30240LDG1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
Dual Channel Precision Universal Clock Generator and NCO
Data Sheet 19
6.0 Detailed Register Map
Register_Address: 0x0
Register Name: Chip_id
Default Value: 0x03100000
Type: R
Bit Field Function Name Description
31:16 Chip_id[15:0] For ZL30240, chip_id = 0x0310
15:0 Reserved Leave as default
Register_Address: 0x1
Register Name: Product_id
Default Value: 7AF000000000
Type: R
Bit Field Function Name Description
31:0 Product_id[31:0] Common value for all ZL3024x products
Register_Address: 0x2
Register Name: Device_config1
Default Value: 0x00AA0A
Type: R/W
Bit Field Function Name Description
23:20 Reserved Leave as default
19 PhaseAlign Toggle this bit to 1 to align the phases of the two PLLs.
Note: A phase hit may result on the output.
18 PhaseAlign_enable If this bit is 0, the PhaseAlign function will be disabled.
If this bit is 1, the PhaseAlign function will be enabled and controlled by
PhaseAlign (bit 19).
17 OERef Output enable for the reference output
16 OERef_override If this bit is 0, the reference output is controlled by the OERef pin.
If this bit is 1, the reference output is controlled by bit 17.
15 OE4 Output 4 enable
14 OE4_override If this bit is 0, output 4 is controlled by the OE4 pin.
If this bit is 1, output 4 is controlled by bit 15.
Dual Channel Precision Universal Clock Generator and NCO
Data Sheet 20
13 OE3 Output 3 enable
12 OE3_override If this bit is 0, output 3 is controlled by the OE3 pin.
If this bit is 1, output 3 is controlled by bit 13.
11 OE2 Output 2 enable
10 OE2_override If this bit is 0, output 2 is controlled by the OE2 pin.
If this bit is 1, output 2 is controlled by bit 11.
9 OE1 Output 1 enable
8 OE1_override If this bit is 0, output 1 is controlled by the OE1 pin.
If this bit is 1, output 1 is controlled by bit 9.
7 Refsel2 Control of PLL2 reference selection multiplexer
Selection:
0 - The input for PLL2 is XO1/XO2.
1 - The input for PLL2 is XO3/XO4 or In_p/In_n in based on xtal2_enable
in Register 0xA
6 Reserved Leave as default (Set to 1)
5 Refsel1 Control of PLL1 reference selection multiplexer
Selection:
0 - The input for PLL1 is XO1/XO2.
1 - The input for PLL1 is XO3/XO4 or In_p/In_n in based on xtal2_enable
in Register 0xA
4 Reserved Leave as default (Set to 1)
3 PU2 Power up PLL2
2 Reserved Leave as default (Set to 1)
1 PU1 Power up PLL1
0 Reserved Leave as default (Set to 1)
Register_Address: 0x2
Register Name: Device_config1
Default Value: 0x00AA0A
Type: R/W
Bit Field Function Name Description
Dual Channel Precision Universal Clock Generator and NCO
Data Sheet 21
Register_Address: 0x3
Register Name: Device_config2
Default Value: 0x100F0000
Type: R/W
Bit Field Function Name Description
31:30 Refmode[1:0] Determine the mode of the reference output (RefOut_p/RefOut_n)
Selection:
0b11 -HCSL (differential)
0b10 -LVPECL (differential)
0b01 -LVDS (differential)
0b00 -LVCMOS (single ended) - default
29:28 Reserved Leave as default (Set to 1)
27 refmux_sel Reference Multiplexer:
Selection:
0 - Reference output from Crystal Input 1 (XO1/XO2)
1 - Reference output from In_p/In_n or Crystal Input 2 (XO3/XO4) based
on xtal2_enable in Register 0xA
26 xtal_enable Enables the XO1/XO2 crystal input 1 function
25 diff_ref_sel Sets the mode for In_p/In_n
Selection:
0 - CMOS (singled ended) - Input signal on In_p
Note: In_n should not be connected
1 - Differential - Input signal on In_p/In_n pair
24 Reserved Leave as default
23:20 Ref_div[3:0] Reference divider is (bits[23:20] + 1)
Range: 1 (0x0) to 16 (0xF)
19 Reserved Leave as default (Set to 1)
18 Reserved Leave as default (Set to 1)
17 Reserved Leave as default (Set to 1)
16 Reserved Leave as default (Set to 1)
15:12 Reserved Leave as default
11 out4_4p5 mode When this bit is 1, an output divisor of 4.5 is selected for output 4
10 out3_4p5 mode When this bit is 1, an output divisor of 4.5 is selected for output 3
9 out2_4p5 mode When this bit is 1, an output divisor of 4.5 is selected for output 2
8 out1_4p5 mode When this bit is 1, an output divisor of 4.5 is selected for output 1
7:0 Reserved Leave as default
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

ZL30240LDG1

Mfr. #:
Buy ZL30240LDG1
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Dual Prec Univ Clock Gen and NCO
Lifecycle:
New from this manufacturer.
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