Dual Channel Precision Universal Clock Generator and NCO
Data Sheet 9
3.0 Description
The ZL30240 is a dual PLL clock generator with four programmable outputs. Two PLLs, each with either a crystal, crystal oscillator
or external reference input frequency, produce up to four unique output frequencies. Each output can select between LVCMOS,
LVDS, LVPECL, and HCSL. The input crystal is a low cost fundamental mode type, and the ZL30240 provides programmable gain
and load capacitors for the crystal inputs. Alternatively, a multi-standard input reference can be used for either or both PLLs with a
dedicated divider. The crystal or external reference frequency are also available as an output bypassing the PLLs for test purposes.
The PLLs operate independently, but may share the input reference. Three modes of operation can be selected: integer mode,
fractional mode, and ratio mode. The integer mode provides lowest noise, and behaves like a conventional PLL with whole number
dividers. This device will get integer mode performance even with 3 fractional bits in use allowing eights in the feedback divider
without increasing the jitter. The fractional mode allows the feedback divider to have an 8 bit integer part and 28 bit fractional part,
resulting in a frequency resolution of 0.1 ppb or better. Finally, the ratio mode offers frequency translation of an N + X/Y nature for
frequency translation applications like SONET and OTN.
The PLLs have VCOs that operate between 3053 MHz and 3677 MHz. There are two output dividers on each PLL, with a range of 4
to 259. In order to prevent a “frequency hole” between 750.6 MHz and 777.5 MHz, a special divide by 4.5 mode is also included.
Any output frequency between 12 MHz and 914 MHz can be produced on the differential output.
Additional features include loss of lock indicators and high speed SPI control. The ZL30240 has factory programmed defaults and
may also be reconfigured through the SPI port.
3.1 Input Configuration
The In_p/In_n pins can take one of four modes.
Table 2 - Input modes
For LVCMOS mode, the external components are shown in Figure 2.
Refmode [1:0] Mode
00 LVCMOS
01 LVDS
10 LVPECL
11 HCSL
CMOS
Driver
VDD_driver
VDD
Z
o
=50Ohms
In_p
In_n
In_VCM
NC
1kohm
Figure 2 - Input Termination - LVCMOS
