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LTC3612EUDC#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
LTC3612
19
3612fc
For more information www.linear.com/LTC3612
AVP Mode
Fast load transient response, limited board space and low
cost are typical requirements of microprocessor power
supplies. A microprocessor has typical full load step with
very fast slew rate. The voltage at the microprocessor must
be held to about ±0.1V of nominal in spite of these load
current steps. Since the control loop cannot respond this
fast, the output capacitors must supply the load current
until the control loop can respond.
Normally, several capacitors in parallel are required to
meet microprocessor transient requirements. Capacitor
ESR and ESL primarily determine the amount of droop or
overshoot in the output voltage.
Consider the LTC3612 without AVP with a bank of tantalum
output capacitors. If a load step with very fast slew rate
occurs, the voltage excursion will be seen in both direc
-
tions, for full load to minimum load transient and for the
minimum load to full load transient.
If the ITH pin is tied to SV
IN
, the active voltage position-
ing (AVP) mode and internal compensation are selected.
AVP mode intentionally compromises load regulation by
reducing the gain of the feedback cir
cuit, resulting in an
output voltage that varies with load current. When the load
current suddenly increases, the output voltage starts from
a level slightly higher than nominal so the output voltage
can droop more and stay within the specified voltage
range. When the load current suddenly decreases the
output voltage starts at a level lower than nominal so the
output voltage can have more overshoot and stay within
the specified voltage range (see Figures 3 and 4).
applicaTions inForMaTion
Figure 4. Load Step Transient Forced Continuous Mode
with AVP Mode
The benefit is a lower peak-to-peak output voltage deviation
for a given load step without having to increase the output
filter capacitance. Alternatively, the output voltage filter
capacitance can be reduced while maintaining the same
peak to peak transient response. Due to the reduced loop
gain in AVP mode, no external compensation is required.
DDR Mode
The LTC3612 can both source and sink current if the MODE
pin is configured to forced continuous mode.
Current sinking is typically limited to 1.5A, for 1MHz
frequency and a 1µH inductor, but can be lower at higher
frequencies and low output voltages. If higher ripple current
can be tolerated, smaller inductor values can increase the
sink current limit. See the Typical Performance Charac
-
teristics curves for more information.
In addition, tying the DDR pin to SV
IN
, lower external
reference voltage and tracking output voltage between
channels are possible. See the Output Voltage Tracking
and External Reference Input sections.
Soft-Start
The RUN pin provides a means to shut down the LTC3612.
Tying the RUN pin to SGND places the LTC3612 in a low
quiescent current shutdown state (I
Q
< 1µA).
The LTC3612 is enabled by pulling the RUN pin high. How-
ever, the applied voltage must not exceed SV
IN
. In some
applications, the RUN signal is generated within another
power domain and is driven high while the SV
IN
and PV
IN
is still 0V. In this case, it’s required to limit the current into
Figure 3. Load Step Transient Forced Continuous Mode
(AVP Inactive)
V
OUT
200mV/DIV
I
L
1A/DIV
50µs/DIV
3612 F03
V
IN
= 3.3V
V
OUT
= 1.8V
I
LOAD
= 100mA TO 3A
V
MODE
= 1.5V
COMPENSATION FIGURE 1
V
OUT
100mV/DIV
I
L
1A/DIV
50µs/DIV
3612 F04
V
IN
= 3.3V
V
OUT
= 1.8V
I
LOAD
= 100mA TO 3A
V
MODE
= 1.5V
V
ITH
= 3.3V
OUTPUT CAPACITOR VALUE FIGURE 1
LTC3612
20
3612fc
For more information www.linear.com/LTC3612
applicaTions inForMaTion
the RUN pin by either adding a 1MΩ resistor or a 100kΩ
resistor, plus a Schottky diode, to SV
IN
. After pulling the
RUN pin high, the chip enters a soft start-up state. This
type of soft start-up behavior is set by the TRACK/SS pin:
1. Tying TRACK/SS to SV
IN
selects the internal soft-start
circuit. This circuit ramps the output voltage to the final
value within 1ms.
2. If a longer soft-start period is desired, it can be set ex
-
ternally with a resistor and capacitor on the TRACK/SS
pin, as shown in Figure 1. The TRACK/SS pin reduces
the value of the internal reference at V
FB
until TRACK/
SS is pulled above 0.6V. The external soft-start duration
can be calculated by using the following formula:
t
SS
= R
SS
•C
SS
•ln
SV
IN
SV
IN
– 0.6V
3. The TRACK/SS pin can be used to track the output
voltage of another supply.
Each time the RUN pin is tied high and the LTC3612 is
turned on, the TRACK/SS pin is internally pulled down
for ten microseconds in order to discharge the external
capacitor. This discharging time is typically adequate for
capacitors up to about 33nF. If a larger capacitor is required,
connect the external soft-start resistor to the RUN pin.
Regardless of either internal or external soft-start state,
the MODE pin is ignored and soft-start will always be in
pulse-skipping mode. In addition, the PGOOD pin is kept
low and foldback of the switching frequency is disabled.
Output Voltage Tracking Input
If the DDR pin is not tied to SV
IN
, once V
TRACK/SS
exceeds
0.6V, the run state is entered and the MODE selection,
power good and current foldback circuits are enabled.
In the run state, the TRACK/SS pin can be used for track
-
ing down/up the output voltage of another supply. If the
V
TRACK/SS
drops below 0.6V, the LTC3612 enters the down
tracking state and V
OUT
is referenced to the TRACK/SS volt-
age. If the TRACK/SS pin drops below 0.2V, the switching
frequency is reduced to ensure that the minimum duty
cycle limit does not prevent the output from following
Figure 5. Two Different Modes of Output Voltage Tracking
TIME
(5b) Ratiometric Tracking
V
OUT1
V
OUT2
OUTPUT VOLTAGE
TIME
3612 F05
(5a) Coincident Tracking
V
OUT1
V
OUT2
OUTPUT VOLTAGE
the TRACK/SS pin. The run state will resume if V
TRACK/SS
again exceeds 0.6V and V
OUT
is referenced to the internal
precision reference (see Figure 7).
Through the TRACK/SS pin, the output voltage can be set
up for either coincident or ratiometric tracking, as shown
in Figure 5.
To implement the coincident tracking behavior in Fig-
ure
5a, connect an extra resistive divider to the output
of the master channel and connect its midpoint to the
TRACK/SS pin for the slave channel. The ratio of this
divider should be selected to be the same as that of the
slave channel’s feedback divider (Figure 6a).
In this track-
ing mode, the master channel’s output must be set higher
than slave channel’s output. T
o implement the ratiometric
tracking behavior in Figure 5b, different resistor divider
values must be used as specified in Figure 6b.
LTC3612
21
3612fc
For more information www.linear.com/LTC3612
applicaTions inForMaTion
For coincident start-up, the voltage value at the TRACK/SS
pin for the slave channel needs to reach the final reference
value after the internal soft-start time (around 1ms). The
master start-up time needs to be adjusted with an external
capacitor and resistor to ensure this.
External Reference Input (DDR Mode)
If the DDR pin is tied to SV
IN
(DDR mode), the run state is
entered when V
TRACK/SS
exceeds 0.3V and tracking down
behavior is possible if the V
TRACK/SS
voltage is below 0.6V.
This allows TRACK/SS to be used as an external reference
between 0.3V and 0.6V if desired. During the run state in
DDR mode, the power good window moves in relation
to the actual TRACK/SS pin voltage if the voltage value
is between 0.3V and 0.6V. Note: if TRACK/SS voltage is
0.6V, either the tracking circuit or the internal reference
can be used.
During up/down tracking the output current foldback is
disabled and the PGOOD pin is always pulled down (see
Figure 8).
Figure 6a. Set-Up for Coincident Tracking
Figure 6b. Set-Up for Ratiometric Tracking
V
FB2
R4
R2
R4
R2
R3
R2
R4 ≤ R3
V
OUT2
V
OUT1
LTC3612
TRACK/SS2
V
FB1
V
IN
LTC3612
LTC3612 CHANNEL 2
SLAVE
LTC3612 CHANNEL 1
MASTER
TRACK/SS1
3612 F06a
V
FB2
R1
R2
R5
R6
R3 R1/R2 < R5/R6
R4
V
OUT2
V
OUT1
LTC3612
TRACK/SS2
V
FB1
V
IN
3612 F06b
LTC3612
LTC3612 CHANNEL 2
SLAVE
LTC3612 CHANNEL 1
MASTER
TRACK/SS1
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent
-
age of input power.
Although
all
dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V
IN
quiescent current and I
2
R losses. The V
IN
quiescent current loss dominates the efficiency loss at
very low load currents whereas the I
2
R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
usually of no consequence.
1. The V
IN
quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
low to high to low again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is the current
out of V
IN
due to gate charge, and it is typically larger
than the DC bias current. Both the DC bias and gate
charge losses are proportional to V
IN
; thus, their effects
will be more pronounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor, R
L
. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
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LTC3612EUDC#PBF

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Buy LTC3612EUDC#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3A, 4MHz, Monolithic Synchronous Step-Down Regulator
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