LTC3612
4
3612fc
For more information www.linear.com/LTC3612
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3612 is tested under pulsed load conditions such that
T
J
≈
T
A
. The LTC3612E is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the
–40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3612I is guaranteed over the full –40°C to 125°C operating
junction temperature range. The LTC3612H is guaranteed to meet
specifications over the –40°C to 150°C operating temperature range. The
LTC3612MP is guaranteed and tested to meet specifications over the full
–55°C to 150°C operating temperature range. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors. The junction
temperature
(T
J
, in °C) is calculated from the ambient temperature (T
A
, in °C) and
power dissipation (P
D
, in watts) according to the formula:
T
J
= T
A
+ (P
D
• θ
JA
),
where θ
JA
(in °C/W) is the package thermal impedance.
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at T
A
= 25°C (Note 2). V
IN
= 3.3V, RT/SYNC = SV
IN
, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PGOOD Power Good Voltage Windows TRACK/SS = SV
IN
, Entering Window
V
FB
Ramping Up
V
FB
Ramping Down
–3.5
3.5
–6
6
%
%
TRACK/SS = SV
IN
, Leaving Window
V
FB
Ramping Up
V
FB
Ramping Down
9
–9
11
–11
%
%
t
PGOOD
Power Good Blanking Time Entering and Leaving Window 70 105 140 µs
R
PGOOD
Power Good Pull-Down On-Resistance 8 17 33 Ω
V
RUN
RUN Voltage Input High
Input Low
l
l
1
0.4
V
V
Note 3: This parameter is tested in a feedback loop which ser
vos V
FB
to
the midpoint for the error amplifier (V
ITH
= 0.75V).
Note 4: External compensation on ITH pin.
Note 5: Tying the ITH pin to SV
IN
enables the internal compensation and
AVP mode.
Note 6: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 7: See description of the TRACK/SS pin in the Pin Functions section.
Note 8: In sourcing mode the average output current is flowing out of SW
pin. In sinking mode the average output current is flowing into the SW Pin.
Note 9: See description of the MODE pin in the Pin Functions section.
Note 10: Guaranteed by correlation and design to wafer level
measurements for QFN packages.
Note 11: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
