PCF8591 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 27 June 2013 20 of 31
NXP Semiconductors
PCF8591
8-bit A/D and D/A converter
14.4 Dynamic characteristics
[1] A detailed description of the I
2
C bus specification, with applications, is given in Ref. 11 “UM10204”.
Table 11. Dynamic characteristics
All timing characteristics are valid within the operating supply voltage and ambient temperature
range and reference to V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
Symbol Parameter Min Typ Max Unit
I
2
C bus timing (see Figure 21)
[1]
f
SCL
SCL clock frequency - - 100 kHz
t
SP
pulse width of spikes that must be
suppressed by the input filter
- - 100 ns
t
BUF
bus free time between a STOP and START
condition
4.7 - - s
t
SU;STA
set-up time for a repeated START condition 4.7 - - s
t
HD;STA
hold time (repeated) START condition 4.0 - - s
t
LOW
LOW period of the SCL clock 4.7 - - s
t
HIGH
HIGH period of the SCL clock 4.0 - - s
t
r
rise time of both SDA and SCL signals - - 1.0 s
t
f
fall time of both SDA and SCL signals - - 0.3 s
t
SU;DAT
data set-up time 250 - - s
t
HD;DAT
data hold time 0 - - s
t
VD;DAT
data valid time - - 3.4 s
t
SU;STO
set-up time for STOP condition 4.0 - - s
Fig 21. I
2
C bus timing diagram; rise and fall times refer to V
IL
and V
IH
PROTOCOL
SCL
SDA
mbd820
BIT 0
LSB
(R/W)
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
t
SU;STA
t
HD;STA
t
SU;DAT
t
HD;DAT
t
VD;DAT
t
SU;STO
t
LOW
t
HIGH
1 / f
SCL
t
BUF
t
r
t
f
