PCF8591 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 27 June 2013 8 of 31
NXP Semiconductors
PCF8591
8-bit A/D and D/A converter
8.4 A/D conversion
The A/D converter uses the successive approximation conversion technique. The on-chip
D/A converter and a high-gain comparator are used temporarily during an A/D conversion
cycle.
An A/D conversion cycle is always started after sending a valid read mode address to a
PCF8591 device. The A/D conversion cycle is triggered at the trailing edge of the
acknowledge clock pulse and is executed while transmitting the result of the previous
conversion (see Figure 8
).
Once a conversion cycle is triggered, an input voltage sample of the selected channel is
stored on the chip and is converted to the corresponding 8-bit binary code. Samples
picked up from differential inputs are converted to an 8-bit two's complement code (see
Figure 9
and Figure 10).
Fig 7. D/A conversion sequence
KLJKLPSHGDQFHVWDWHRI
SUHYLRXVYDOXHKHOGLQ'$&UHJLVWHU
SUHYLRXVYDOXHKHOG
LQ'$&UHJLVWHU
6
$ $&21752/%<7( $'$7$%<7( $'$7$%<7($''5(66
Fig 8. A/D conversion sequence
S 1 A A A AADDRESS DATA BYTE 1 DATA BYTE 2DATA BYTE 0
12 981 91 91
protocol
SCL
SDA
conversion of byte 2 conversion of byte 3conversion of byte 1
transmission
of previously
converted byte
sampling byte 2 sampling byte 3sampling byte 1
transmission
of byte 1
transmission
of byte 2
mbl829
