PCF8591 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 27 June 2013 5 of 31
NXP Semiconductors
PCF8591
8-bit A/D and D/A converter
8. Functional description
8.1 Addressing
Each PCF8591 device in an I
2
C-bus system is activated by sending a valid address to the
device. The address consists of a fixed part and a programmable part. The programmable
part must be set according to the address pins A0, A1 and A2. The address is always sent
as the first byte after the start condition in the I
2
C-bus protocol. The last bit of the address
byte is the read/write-bit which sets the direction of the following data transfer (see Table 5
on page 13, Figure 15 on page 13 and Figure 16 on page 13).
8.2 Control byte
The second byte sent to a PCF8591 device is stored in its control register and is required
to control the device function. The upper nibble of the control register is used for enabling
the analog output, and for programming the analog inputs as single-ended or differential
inputs. The lower nibble selects one of the analog input channels defined by the upper
nibble (see Figure 4
). If the auto-increment flag is set, the channel number is incremented
automatically after each A/D conversion.
If the auto-increment mode is desired in applications where the internal oscillator is used,
the analog output enable flag must be set in the control byte (bit 6). This allows the
internal oscillator to run continuously, by this means preventing conversion errors
resulting from oscillator start-up delay. The analog output enable flag can be reset at other
times to reduce quiescent power consumption.
The selection of a non-existing input channel results in the highest available channel
number being allocated. Therefore, if the auto-increment flag is set, the next selected
channel is always channel 0. The most significant bits of both nibbles are reserved for
possible future functions and must be set to logic 0. After a Power-On Reset (POR)
condition, all bits of the control register are reset to logic 0. The D/A converter and the
oscillator are disabled for power saving. The analog output is switched to a
high-impedance state.
