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MT40A1G16WBU-075E:B

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
10. When CA parity is enabled for I
DD2N
, current changes by approximately +7%.
11. I
PP3N
test and limit is applicable for all I
DD2x
, I
DD3x
, I
DD4x
, I
DD6x
, and I
DD8
conditions; that
is, testing I
PP3N
should satisfy the I
PP
s for the noted I
DD
tests.
12. When additive latency is enabled for I
DD3N
, current changes by approximately +0.6%.
13. When additive latency is enabled for I
DD4R
, current changes by approximately +5%.
14. When read DBI is enabled for I
DD4R
, current changes by approximately 0%.
15. When additive latency is enabled for I
DD4W
, current changes by approximately +4%.
16. When write DBI is enabled for I
DD4W
, current changes by approximately 0%.
17. When write CRC is enabled for I
DD4W
, current changes by approximately –3%.
18. When CA parity is enabled for I
DD4W
, current changes by approximately +12%.
19. When 2X REF is enabled for I
DD5R
, current changes by approximately –14%.
20. When 4X REF is enabled for I
DD5R
, current changes by approximately –33%.
21. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature
range of operation (0–85°C).
22. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended tempera-
ture range of operation (0–95°C).
23. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature
range of operation (0–45°C).
24. I
DD6R
and I
DD6A
values are typical.
Table 10: x16 I
DD
, I
PP
, and I
DDQ
Current Limits – Rev. D
Symbol DDR4-2133
1
DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit Notes
I
DD0
: One bank ACTIVATE-to-
PRECHARGE current
90 96 102 108 114 mA 2, 3, 4
I
PP0
: One bank ACTIVATE-to-
PRECHARGE I
PP
current
6 6 6 6 6 mA
I
DD1
: One bank ACTIVATE-to-
READ-to-PRECHARGE current
114 120 126 132 138 mA 3, 4, 5
I
DD2N
: Precharge standby cur-
rent
66 68 70 72 74 mA 4, 6, 7,
8, 9, 10,
11
I
DD2NT
: Precharge standby
ODT current
90 100 100 110 120 mA 4, 11
I
DD2P
: Precharge power-down
current
50 50 50 50 50 mA 4, 11
I
DD2Q
: Precharge quiet stand-
by current
60 60 60 60 60 mA 4, 11
I
DD3N
: Active standby current 90 96 102 108 112 mA 4, 11
I
PP3N
: Active standby I
PP
cur-
rent
6 6 6 6 6 mA
I
DD3P
: Active power-down cur-
rent
70 74 78 82 86 mA 4, 11
I
DD4R
: Burst read current 250 270 292 314 336 mA 4, 14,
13, 11
I
DD4W
: Burst write current 250 264 284 300 320 mA 4, 11,
15, 16,
17, 18
16Gb: x16 TwinDie Single Rank DDR4 SDRAM
Current Specifications – Limits
CCMTD-1725822587-9947
16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Table 10: x16 I
DD
, I
PP
, and I
DDQ
Current Limits – Rev. D (Continued)
Symbol DDR4-2133
1
DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit Notes
I
DD5R
: Distributed refresh cur-
rent (1X REF)
112 116 122 128 132 mA 4, 19, 20
I
PP5R
: Distributed refresh I
PP
current (1X REF)
10 10 10 10 10 mA
I
DD6N
: Self refresh current; 0–
85°C
62 62 62 62 62 mA 11, 21
I
DD6E
: Self refresh current; 0–
95°C
72 72 72 72 72 mA 11, 22
I
DD6R
: Self refresh current; 0–
45°C
42 42 42 42 42 mA 11, 23,
24
I
DD6A
: Auto self refresh cur-
rent (25°C)
17.2 17.2 17.2 17.2 17.2 mA 11, 24
I
DD6A
: Auto self refresh cur-
rent (45°C)
42 42 42 42 42 mA 11, 24
I
DD6A
: Auto self refresh cur-
rent (75°C)
62 62 62 62 62 mA 11, 24
I
PP6X
: Auto self refresh current
I
PP
current
10 10 10 10 10 mA 11, 24
I
DD7
: Bank interleave read cur-
rent
340 350 360 370 380 mA 4
I
PP7
: Bank interleave read I
PP
current
30 30 30 30 30 mA
I
DD8
: Maximum power-down
current
50 50 50 50 50 mA 11
Notes:
1. DDR4-1600 and DDR4-1866 use the same I
DD
limits as DDR4-2133.
2. When additive latency is enabled for I
DD0
, current changes by approximately 0%.
3. I
PP0
test and limit is applicable for I
DD0
and I
DD1
conditions.
4. The I
DD
values must be derated (increased) when operated outside of the range 0°C ≤ T
C
≤ 85°C:
When T
C
< 0°C: I
DD2P
and I
DD3P
must be derated by 6%; I
DD4R
and I
DD4W
must be derated
by +4%; and I
DD7
must be derated by +11%.
When T
C
> 85°C: I
DD0
, I
DD1
, I
DD2N
, I
DD2NT
, I
DD2Q
, I
DD3N
, I
DD3P
, I
DD4R
, I
DD4W
, and I
DD5R
must
be derated by +3%; I
DD2P
must be derated by +40%.
5. When additive latency is enabled for I
DD1
, current changes by approximately +4%.
6. When additive latency is enabled for I
DD2N
, current changes by approximately 0%.
7. When DLL is disabled for I
DD2N
, current changes by approximately –23%.
8. When CAL is enabled for I
DD2N
, current changes by approximately –25%.
9. When gear-down is enabled for I
DD2N
, current changes by approximately 0%.
10. When CA parity is enabled for I
DD2N
, current changes by approximately +7%.
11. I
PP3N
test and limit is applicable for all I
DD2x
, I
DD3x
, I
DD4x
, I
DD6x
, and I
DD8
conditions; that
is, testing I
PP3N
should satisfy the I
PP
s for the noted I
DD
tests.
12. When additive latency is enabled for I
DD3N
, current changes by approximately +0.6%.
13. When additive latency is enabled for I
DD4R
, current changes by approximately +5%.
16Gb: x16 TwinDie Single Rank DDR4 SDRAM
Current Specifications – Limits
CCMTD-1725822587-9947
16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN
17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
14. When read DBI is enabled for I
DD4R
, current changes by approximately 0%.
15. When additive latency is enabled for I
DD4W
, current changes by approximately +4%.
16. When write DBI is enabled for I
DD4W
, current changes by approximately 0%.
17. When write CRC is enabled for I
DD4W
, current changes by approximately –3%.
18. When CA parity is enabled for I
DD4W
, current changes by approximately +12%.
19. When 2X REF is enabled for I
DD5R
, current changes by approximately –14%.
20. When 4X REF is enabled for I
DD5R
, current changes by approximately –33%.
21. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature
range of operation (0–85°C).
22. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended tempera-
ture range of operation (0–95°C).
23. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature
range of operation (0–45°C).
24. I
DD6R
and I
DD6A
values are typical.
Table 11: x16 I
DD
, I
PP
, and I
DDQ
Current Limits – Rev. E
Symbol DDR4-2133
1
DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit Notes
I
DD0
: One bank ACTIVATE-to-
PRECHARGE current
78 82 86 90 94 mA 2, 3, 4
I
PP0
: One bank ACTIVATE-to-
PRECHARGE I
PP
current
6 6 6 6 6 mA
I
DD1
: One bank ACTIVATE-to-
READ-to-PRECHARGE current
110 114 118 122 126 mA 3, 4, 5
I
DD2N
: Precharge standby cur-
rent
58 60 62 64 66 mA 4, 6, 7, 8,
9, 10, 11
I
DD2NT
: Precharge standby ODT
current
72 76 80 84 88 mA 4, 11
I
DD2P
: Precharge power-down
current
44 44 44 44 44 mA 4, 11
I
DD2Q
: Precharge quiet standby
current
52 52 52 52 52 mA 4, 11
I
DD3N
: Active standby current 70 74 78 82 86 mA 4, 11
I
PP3N
: Active standby I
PP
current 6 6 6 6 6 mA
I
DD3P
: Active power-down cur-
rent
58 60 62 64 66 mA 4, 11
I
DD4R
: Burst read current 270 290 312 334 356 mA 4, 14, 13,
11
I
DD4W
: Burst write current 228 246 264 282 300 mA 4, 11, 15,
16, 17,
18
I
DD5R
: Distributed refresh cur-
rent (1X REF)
92 94 96 98 100 mA 4, 19, 20
I
PP5R
: Distributed refresh I
PP
current (1X REF)
10 10 10 10 10 mA
I
DD6N
: Self refresh current; 0–
85°C
68 68 68 68 68 mA 11, 21
16Gb: x16 TwinDie Single Rank DDR4 SDRAM
Current Specifications – Limits
CCMTD-1725822587-9947
16gb_x16_1cs_TwinDie.pdf - Rev. G 06/18 EN
18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

MT40A1G16WBU-075E:B

Mfr. #:
Buy MT40A1G16WBU-075E:B
Manufacturer:
Micron
Description:
IC DRAM 16G PARALLEL 1.33GHZ
Lifecycle:
New from this manufacturer.
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