LT3582/LT3582-5/LT3582-12
19
3582512fb
Maximum Load Currents: Use one of the following equa-
tions to estimate the maximum output load current for the
positive and negative output voltages:
I
OUTP
=
V
IN(MIN)
V
OUTP
I
PK
T
OFF _MIN
•(V
OUTP
+ 0.5 – V
IN(MIN)
)
2•L
0.8η
or I
OUTN
=
V
IN(MIN)
V
IN(MIN)
+|V
OUTN
|
I
PK
T
OFF _MIN
•(|V
OUTN
| +0.5)
2•L
0.8η
where:
V
OUT
= Regulation voltage
V
IN(MIN)
= Minimum input voltage.
I
PK
= Peak inductor current. See the
Peak
Current Rating
section. Use minimum
I
LIMIT
rating for these calculations.
η = Power conversion effi ciency (about 88%
for Boost or 78% for Inverting)
T
OFF_MIN
= Minimum switch off time. Typically 100ns
for Boost and 125ns for Inverting.
I
OUT
= Output load current
For example, if V
OUTP
= 10V, V
OUTN
= –10V, V
IN
= 5V, and
L = 4.7H then I
OUTP
= 117mA and I
OUTN
= 105mA.
Note: The 155mA (Typ) current limit of the output dis-
connect PMOS (see Electrical Characteristics) may limit
maximum I
OUTP
unless CAPP is shorted to V
OUTP
. See the
Improving Boost Converter Effi ciency
section.
Maximum Slew Rate: Lower inductance causes higher
current slew rates which can lead to current limit over-
shoot. Choose an inductance higher than L
MIN
to limit
the overshoot:
L
MIN
= V
IN(MAX)
• 0.2µH
where V
IN(MAX)
is the maximum input voltage. Using the
previous example V
IN
= 3V, L
MIN
= 0.6H.
Capacitor Selection
The small size and low ESR of ceramic capacitors makes
them suitable for most LT3582 series applications. X5R
and X7R types are recommended because they retain their
capacitance over wider voltage and temperature ranges
than other types such as Y5V or Z5U. A 4.7F input capaci-
tor and a 2.2F to 10F output capacitor are suffi cient for
most LT3582 series applications. Always use a capacitor
with a suffi cient voltage rating. Many capacitors rated at
2.2F to 10F, particularly 0805 or 0603 case sizes, have
greatly reduced capacitance at the desired output voltage.
Generally a 1206 capacitor will be adequate. A 0.22F to
1F capacitor placed on the CAPP node is recommended
to fi lter the inductor current while the larger 2.2F to 10F
placed on the V
OUTP
and V
OUTN
nodes will give excellent
transient response and stability. Avoid placing large value
capacitors (generally > 6.8F) on both CAPP and V
OUTP
.
This confi guration can be less stable since it creates two
poles, one at the CAPP pin and the other at the V
OUTP
pin, which can be near each other in frequency. Table 4
shows a list of several capacitor manufacturers. Consult
the manufacturers for more detailed information and for
their entire selection of related parts.
Table 4. Ceramic Capacitor Manufacturers
MANUFACTURER PHONE URL
Kemet 408-986-0424 www.kemet.com
Murata 814-237-1431 www.murata.com
Taiyo Yuden 408-573-4150 www.t-yuden.com
TDK 847-803-6100 www.tdk.com
Diode Selection
Schottky diodes, with their low forward voltage drops and
fast switching speeds, are recommended for use with the
LT3582 series. The Diodes Inc. B0540WS is a very good
choice in a small SOD-323 package. This diode is rated to
handle an average forward current of 500mA and performs
well across a wide temperature range. Schottky diodes
with very low forward voltage drops are also available.
These diodes may improve effi ciency at moderate and cold
temperatures, but will likely reduce effi ciency at higher
temperatures due to excessive reverse leakage currents.
APPLICATIONS INFORMATION
LT3582/LT3582-5/LT3582-12
20
3582512fb
Output Disconnect Operating Limits
The LT3582 series has a PMOS output disconnect switch
connected between CAPP and V
OUTP
. During normal
operation, the switch is closed and current is internally
limited to about 155mA (see Figure 9). Make sure that the
output load current doesn’t exceed the PMOS current limit.
Exceeding the current limit causes a signifi cant rise in PMOS
power consumption which may damage the device.
During shutdown, the PMOS switch is open and CAPP is
isolated from V
OUTP
up to a voltage difference of 5-5.5V.
In most cases this allows V
OUTP
to discharge to ground.
However, when the Boost inductor input exceeds 5.5V, the
CAPP-V
OUTP
voltage may exceed 5V allowing some current
ow through the PMOS switch. In addition, applying CAPP-
V
OUTP
voltages in excess of 5.7V(typical) may activate
internal protection circuitry which turns the PMOS “on”
(see Figure 10). If the current is not limited, this can lead
to a sharp increase in the PMOS power consumption and
may damage the device. If this situation cannot be avoided,
limit PMOS power consumption to less than 1/3 Watt (about
50mA at 7V) to avoid damaging the device. Refer to the
Absolute Maximum Ratings table for maximum limits on
CAPP-V
OUTP
voltages and currents.
Improving Boost Converter Effi ciency
The effi ciency of the Boost converter can be improved by
shorting the CAPP pin to the V
OUTP
pin (see Figure 11). The
power loss in the PMOS disconnect circuit is then made
negligible. In most applications, the associated CAPP pin
capacitor can be removed and the larger V
OUTP
capacitor
can adequately fi lter the output voltage.
APPLICATIONS INFORMATION
LT3582
V
IN
CAPP
CAPP
V
OUTP
SDA
V
PP
CASHDN
GND
SWN
SWN
V
OUTN
3582512 F12
SCL
SWP
81
16
15
14
9
10
11
5
12
76
2
13
3
4
RAMPNRAMPP
C1
I
LOAD
Figure 10. PMOS Current vs Voltage During Shutdown
Figure 11. Improved Effi ciency
I
CAPP-VOUTP
20µA/DIV
V
CAPP-VOUTP
1V/DIV
3582512 F11
Figure 9. PMOS Current vs Voltage During Normal Operation
CAPP-V
OUTP
(mV)
0 100 200 400300 500
0
20
40
100
80
120
140
60
160
180
PMOS CURRENT (mA)
3582512 F10
LT3582/LT3582-5/LT3582-12
21
3582512fb
APPLICATIONS INFORMATION
Note that the ripple voltage on V
OUTP
will typically increase
in this confi guration since the output disconnect PMOS,
when not shorted, helps to create an RC fi lter at the
output. Also, if the V
OUTP
pin is shorted to CAPP, the
power-down discharge should not be enabled. V
OUTP
cannot be discharged to ground during shutdown due to
the path from V
IN
to V
OUTP
through the external inductor
and diode. Finally, due to the path from V
IN
to V
OUTP
,
current will fl ow through the integrated feedback resistor
whenever voltage is present on V
IN
.
Inrush Current
When the Boost inductor input voltage (usually V
IN
) is
stepped from ground to the operating voltage, a high
level of inrush current may fl ow through the inductor
and Schottky diode into the CAPP capacitor. Conditions
that increase inrush current include a larger more abrupt
voltage step at the inductor input, larger CAPP capacitors
and inductors with low inductances and/or low saturation
currents. For circuits that use output capacitor values within
the recommended range and have input voltages of less
than 5V, inrush current remains low, posing no hazard to
the devices. In cases where there are large input voltage
steps (more than 5V) and/or a large CAPP capacitor is
used, inrush current should be measured to ensure safe
operation.
Thermal Lockout
If the die temperature reaches approximately 147°C, the
part will go into thermal lockout. In this event, the chip
is reset which turns off the power switches and starts to
discharge the RAMP capacitors. The part will be re-enabled
when the die temperature drops by about 3.5°C.
Board Layout Considerations
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement. To
maximize effi ciency, switch rise and fall times are made as
short as possible. To prevent electromagnetic interference
(EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signals of the
SWP and SWN pins have sharp rising and falling edges.
Minimize the length and area of all traces connected to
the SWP/SWN pins and always use a ground plane under
the switching regulator to minimize interplane coupling.
Suggested component placement is shown in Figure 12.
Make sure to include the ground plane cuts as shown in
Figure 12. The switching action of the regulators can cause
large current steps in the ground plane. The cuts reduce
noise by recombining the current steps into a continuous
ow under the chip, thus reducing di/dt related ground
noise in the ground plane.
Figure 12. Suggested Component Placement (Not to Scale)
GROUND PLANE
VIAS TO GROUND PLANE UNDER
PIN 17 REQUIRED TO IMPROVE
THERMAL PERFORMANCE
3582512 F13
V
OUTP
C
OUTP
C
CAPP
C
OUTN
V
OUTN
GND
V
IN
C
IN
C
VPP
(OPT)
CA
16
1
2
3
4
56 7 8
15 14 13
12
11
10
9
SCL SDA VPP
L1
L2
17
SHDN

LT3582EUD-5#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Programmable Boost and Single Inductor Inverting DC/DC Converters with OTP
Lifecycle:
New from this manufacturer.
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