AD1928
Rev. B | Page 21 of 32
ALRCLK
ABCLK
2 ADC CHANNELS OF
SECOND IC IN THE CHAIN
2 ADC CHANNELS OF
FIRST IC IN THE CHAIN
UNUSED UNUSED ADC L1 ADC R1 UNUSED UNUSED ADC L1 ADC R1
ADCTDMOUT (TDM_OUT
OF THE SECOND AD1928
IN THE CHAIN)
UNUSED UNUSED ADC L1 ADC R1
ASDATA1 (TDM_IN
OF THE SECOND AD1928
IN THE CHAIN)
32 BITS
MSB
DSP
SECOND
AD1928
FIRST
AD1928
06623-022
Figure 22. ADC TDM Daisy-Chain Mode (512 f
S
BCLK, Two-AD1928 Daisy Chain)
LRCLK
BCLK
SDAT
A
LRCLK
BCLK
SDAT
A
LRCLK
BCLK
SDAT
A
LSB LSB
LSB
LSB
LSB LSB
LEFT CHANNEL RIGHT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
LEFT CHANNEL RIGHT CHANNEL
MSB MSB
MSB
MSB
MSB MSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
I
2
S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LRCLK
BCLK
SDAT
A
LSB LSB
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT
f
S
EXCEPT FOR DSP MODE WHICH, IS 2 ×
f
S
.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
MSB MSB
1/
f
S
06623-023
Figure 23. Stereo Serial Modes
AD1928
Rev. B | Page 22 of 32
DBCLK
DLRCLK
DSDATA
LEFT-JUSTIFIED
MODE
DSDATAx
RIGHT-JUSTIFIED
MODE
DSDATAx
I
2
S-JUSTIFIED
MODE
t
DLH
t
DBH
t
DBL
t
DLSKEW
t
DLS
t
DBP
t
DDS
MSB
MSB
MSB LSB
MSB – 1
t
DDH
t
DDS
t
DDH
t
DDS
t
DDH
t
DDH
t
DDS
06623-024
Figure 24. DAC Serial Timing
ABCLK
ALRCLK
ASDATA
LEFT-JUSTIFIED
MODE
ASDATA
RIGHT-JUSTIFIED
MODE
ASDATA
I
2
S-JUSTIFIED
MODE
t
ABH
LSB
MSB
MSB
MSB
MSB – 1
t
ABL
t
ALS
t
ABDD
t
ABDD
t
ABDD
t
ALH
t
ALSKEW
6623-025
Figure 25. ADC Serial Timing
AD1928
Rev. B | Page 23 of 32
Table 13. Pin Function Changes in TDM-AUX Mode (Replication of Table 12)
Mnemonic Stereo Modes TDM Modes AUX Modes
ADCTDMOUT NC ADC TDM Data Output TDM Data Output
ASDATA1 ADC1 Data Output ADC TDM Data Input AUX Data Output 1 (to External DAC 1)
DSDATA1 DAC1 Data Input DAC TDM Data Input
TDM Data Input
DSDATA2 DAC2 Data Input DAC TDM Data Output
AUX Data Input 1 (from External ADC 1)
DSDATA3 DAC3 Data Input DAC TDM Data Input 2 (Dual-Line Mode)
AUX Data Input 2 (from External ADC 2)
DSDATA4 DAC4 Data Input DAC TDM Data Output 2 (Dual-Line Mode)
AUX Data Output 2 (to External. DAC 2)
ALRCLK ADC LRCLK Input/Output ADC TDM Frame Sync Input/Output
TDM Frame Sync Input/Output
ABCLK ADC BCLK Input/Output ADC TDM BCLK Input/Output
TDM BCLK Input/Output
DLRCLK DAC LRCLK Input/Output DAC TDM Frame Sync Input/Output
AUX LRCLK Input/Output
DBCLK DAC BCLK Input/Output DAC TDM BCLK Input/Output AUX BCLK Input/Output
AUX
ADC 1
LRCLK
BCLK
DATA
MCLK
AUX
ADC 2
LRCLK
BCLK
DATA
MCLK
AUX
DAC 1
AUX
DAC 2
LRCLK
BCLK
DATA
MCLK
LRCLK
BCLK
DATA
MCLK
30MHz
12.288MHz
SHARC IS RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
SHARC
AD1928
TDM MASTER
AUX MASTER
FSYNC-TDM (RFS)
RxCLK
RxDATA
TxCLK
TxDATA
TFS (NC)
ASDATA1
DSDATA4
DBCLK
DLRCLK
DSDATA2
DSDATA3
MCLKI/XI
ADCTDMOUT
ALRCLK ABCLK DSDATA1
06623-026
Figure 26. Example of AUX Mode Connection to SHARC® (AD1928 as TDM Master/AUX Master Shown)

AD1928YSTZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs 2-8-Audio codec w/on chip PLL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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