AD1928
Rev. B | Page 29 of 32
ADDITIONAL MODES
The AD1928 offers several additional modes for board-level
design enhancements. To reduce the EMI in board-level design,
serial data can be transmitted without an explicit BCLK. See
Figure 27 for an example of a DAC TDM data transmission
mode that does not require high speed DBCLK. This configura-
tion is applicable when the AD1928 master clock is generated
by the PLL with the DLRCLK as the PLL reference frequency.
To relax the requirement for the setup time of the AD1928 in
cases of high speed TDM data transmission, the AD1928 can
latch in the data using the falling edge of DBCLK. This
effectively dedicates the entire BCLK period to the setup time.
This mode is useful in cases where the source has a large delay
time in the serial data driver. Figure 28 shows this pipeline
mode of data transmission.
Both the BCLK-less and pipeline modes are available on the
ADC serial data port.
DLRCLK
INTERNAL
DBCLK
DSDATAx
DLRCLK
INTERNAL
DBCLK
DM-DSDATAx
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06623-027
Figure 27. Serial DAC Data Transmission in TDM Format without DBCLK
(Applicable only if PLL locks to DLRCLK. This mode is also available in the ADC serial data port.)
DLRCLK
DBCLK
DSDATAx
DATA MUST BE VALID
AT THIS BCLK EDGE
MSB
6623-028
Figure 28. I
2
S Pipeline Mode in DAC Serial Data Transmission
(Applicable in stereo and TDM, useful for high frequency TDM transmission. This mode is also available in the ADC serial data port.)
