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AD1928YSTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
AD1928
Rev. B | Page 24 of 32
CONTROL REGISTERS
DEFINITIONS
The global address for the AD1928 is 0x04, shifted left one bit due to the R/
W
bit. All registers are reset to 0, except for the DAC volume
registers that are set to full volume. Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Global Address R/
W
Register Address Data
Bit
23:17 16 15:8 7:0
Table 15. Register Addresses and Functions
Address Function
0 PLL and Clock Control 0
1 PLL and Clock Control 1
2 DAC Control 0
3 DAC Control 1
4 DAC Control 2
5 DAC individual channel mutes
6 DAC 1L volume control
7 DAC 1R volume control
8 DAC 2L volume control
9 DAC 2R volume control
10 DAC 3L volume control
11 DAC 3R volume control
12 DAC 4L volume control
13 DAC 4R volume control
14 ADC Control 0
15 ADC Control 1
16 ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0 Register
Bit Value Function Description
0 0 Normal operation PLL power-down
1 Power-down
2:1 00 Input 256 (×44.1 kHz or 48 kHz) MCLKI/XI pin functionality (PLL active), master clock rate setting
01 Input 384 (×44.1 kHz or 48 kHz)
10 Input 512 (×44.1 kHz or 48 kHz)
11 Input 768 (×44.1 kHz or 48 kHz)
4:3 00 XTAL oscillator enabled MCLKO/XO pin, master clock rate setting
01 256 × f
S
VCO output
10 512 × f
S
VCO output
11 Off
6:5 00 MCLKI/XI PLL input
01 DLRCLK
10 ALRCLK
11 Reserved
7 0 Disable: ADC and DAC idle Internal master clock enable
1 Enable: ADC and DAC active
AD1928
Rev. B | Page 25 of 32
Table 17. PLL and Clock Control 1 Register
Bit Value Function Description
0 0 PLL clock DAC clock source select
1 MCLK
1 0 PLL clock ADC clock source select
1 MCLK
2 0 Enabled On-chip voltage reference
1 Disabled
3 0 Not locked PLL lock indicator (read only)
1 Locked
7:4 0000 Reserved
DAC CONTROL REGISTERS
Table 18. DAC Control 0 Register
Bit Value Function Description
0 0 Normal operation Power-down
1 Power-down
2:1 00 32 kHz/44.1 kHz/48 kHz Sample rates
01 64 kHz/88.2 kHz/96 kHz
10 128 kHz/176.4 kHz/192 kHz
11 Reserved
5:3 000 1 SDATA delay (BCLK periods)
001 0
010 8
011 12
100 16
101 Reserved
110 Reserved
111 Reserved
7:6 00 Stereo (normal) Serial format
01 TDM (daisy chain)
10 DAC AUX mode (ADC-, DAC-, TDM-coupled)
11 Dual-line TDM
Table 19. DAC Control 1 Register
Bit Value Function Description
0 0 Latch in midcycle (normal) BCLK active edge (TDM in)
1 Latch in at end of cycle (pipeline)
2:1 00 64 (2 channels) BCLKs per frame
01 128 (4 channels)
10 256 (8 channels)
11 512 (16 channels)
3 0 Left low LRCLK polarity
1 Left high
4 0 Slave LRCLK master/slave
1 Master
5 0 Slave BCLK master/slave
1 Master
6 0 DBCLK pin BCLK source
1 Internally generated
7 0 Normal BCLK polarity
1 Inverted
AD1928
Rev. B | Page 26 of 32
Table 20. DAC Control 2 Register
Bit Value Function Description
0 0 Unmute Master mute
1 Mute
2:1 00 Flat De-emphasis (32 kHz/44.1 kHz/48 kHz mode only)
01 48 kHz curve
10 44.1 kHz curve
11 32 kHz curve
4:3 00 24 Word width
01 20
10 Reserved
11 16
5 0 Noninverted DAC output polarity
1 Inverted
7:6 00 Reserved
Table 21. DAC Individual Channel Mutes
Bit Value Function Description
0 0 Unmute DAC 1L mute
1 Mute
1 0 Unmute DAC 1R mute
1 Mute
2 0 Unmute DAC 2L mute
1 Mute
3 0 Unmute DAC 2R mute
1 Mute
4 0 Unmute DAC 3L mute
1 Mute
5 0 Unmute DAC 3R mute
1 Mute
6 0 Unmute DAC 4L mute
1 Mute
7 0 Unmute DAC 4R mute
1 Mute
Table 22. DAC Volume Controls
Bit Value Function Description
7:0 0 No attenuation DAC volume control
1 to 254 −3/8 dB per step
255 Full attenuation
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

AD1928YSTZ

Mfr. #:
Buy AD1928YSTZ
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs 2-8-Audio codec w/on chip PLL
Lifecycle:
New from this manufacturer.
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