OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD1928YSTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
AD1928
Rev. B | Page 6 of 32
DIGITAL FILTERS
Table 6.
Parameter Mode Factor Min Typ Max Unit
ADC DECIMATION FILTER
All modes, typ @ 48 kHz
Pass Band 0.4375 f
S
21 kHz
Pass-Band Ripple ±0.015 dB
Transition Band 0.5 f
S
24 kHz
Stop Band 0.5625 f
S
27 kHz
Stop-Band Attenuation 79 dB
Group Delay 22.9844/f
S
479 μs
DAC INTERPOLATION FILTER
Pass Band 48 kHz mode, typ @ 48 kHz 0.4535 f
S
22 kHz
96 kHz mode, typ @ 96 kHz 0.3646 f
S
35 kHz
192 kHz mode, typ @ 192 kHz 0.3646 f
S
70 kHz
Pass-Band Ripple 48 kHz mode, typ @ 48 kHz ±0.01 dB
96 kHz mode, typ @ 96 kHz ±0.05 dB
192 kHz mode, typ @ 192 kHz ±0.1 dB
Transition Band 48 kHz mode, typ @ 48 kHz 0.5 f
S
24 kHz
96 kHz mode, typ @ 96 kHz 0.5 f
S
48 kHz
192 kHz mode, typ @ 192 kHz 0.5 f
S
96 kHz
Stop Band 48 kHz mode, typ @ 48 kHz 0.5465 f
S
26 kHz
96 kHz mode, typ @ 96 kHz 0.6354 f
S
61 kHz
192 kHz mode, typ @ 192 kHz 0.6354 f
S
122 kHz
Stop-Band Attenuation 48 kHz mode, typ @ 48 kHz 70 dB
96 kHz mode, typ @ 96 kHz 70 dB
192 kHz mode, typ @ 192 kHz 70 dB
Group Delay 48 kHz mode, typ @ 48 kHz 25/f
S
521 μs
96 kHz mode, typ @ 96 kHz 11/f
S
115 μs
192 kHz mode, typ @ 192 kHz 8/f
S
42 μs
TIMING SPECIFICATIONS
−40°C < T
C
< 125°C, DVDD = 3.3 V ± 10%.
Table 7.
Parameter Condition Comments Min Max Unit
INPUT MASTER CLOCK (MCLK) AND
RESET
t
MH
MCLK duty cycle
DAC/ADC clock source = PLL clock @ 256 f
S
,
384 f
S
, 512 f
S
, and 768 f
S
40 60 %
DAC/ADC clock source = direct MCLK @ 512 f
S
(bypass on-chip PLL)
40 60 %
f
MCLK
MCLK frequency PLL mode, 256 f
S
reference 6.9 13.8 MHz
Direct 512 f
S
mode 27.6 MHz
t
PDR
RST
low
15 ns
t
PDRR
RST
recovery
Reset to active output 4096 t
MCLK
PLL
Lock Time
MCLK and LR
clock input
10 ms
256 f
S
VCO Clock Output Duty Cycle MCLKO/XO pin 40 60 %
AD1928
Rev. B | Page 7 of 32
Parameter Condition Comments Min Max Unit
SPI PORT See Figure 11, except where otherwise noted
t
CCH
CCLK high 35 ns
t
CCL
CCLK low 35 ns
f
CCLK
CCLK frequency f
CCLK
= 1/t
CCP
, only t
CCP
shown in Figure 11 10 MHz
t
CDS
CIN setup To CCLK rising 10 ns
t
CDH
CIN hold From CCLK rising 10 ns
t
CLS
CLATCH
setup
To CCLK rising 10 ns
t
CLH
CLATCH
hold
From CCLK falling 10 ns
t
CLHIGH
CLATCH
high
Not shown in Figure 11 10 ns
t
COE
COUT enable From CCLK falling 30 ns
t
COD
COUT delay From CCLK falling 30 ns
t
COH
COUT hold From CCLK falling, not shown in Figure 11 30 ns
t
COTS
COUT tristate From CCLK falling 30 ns
DAC SERIAL PORT See Figure 24
t
DBH
DBCLK high Slave mode 10 ns
t
DBL
DBCLK low Slave mode 10 ns
t
DLS
DLRCLK setup To DBCLK rising, slave mode 10 ns
t
DLH
DLRCLK hold From DBCLK rising, slave mode 5 ns
t
DLSKEW
DLRCLK skew From DBCLK falling, master mode −8 +8 ns
t
DDS
DSDATA setup To DBCLK rising 10 ns
t
DDH
DSDATA hold From DBCLK rising 5 ns
ADC SERIAL PORT See Figure 25
t
ABH
ABCLK high Slave mode 10 ns
t
ABL
ABCLK low Slave mode 10 ns
t
ALS
ALRCLK setup To ABCLK rising, slave mode 10 ns
t
ALH
ALRCLK hold From ABCLK rising, slave mode 5 ns
t
ALSKEW
ALRCLK skew From ABCLK falling, master mode −8 +8 ns
t
ABDD
ASDATA delay From ABCLK falling 18 ns
AUXILIARY INTERFACE
t
AXDS
AAUXDATA setup To AUXBCLK rising 10 ns
t
AXDH
AAUXDATA hold From AUXBCLK rising 5 ns
t
DXDD
DAUXDATA delay From AUXBCLK falling 18 ns
t
XBH
AUXBCLK high 10 ns
t
XBL
AUXBCLK low 10 ns
t
DLS
AUXLRCLK setup To AUXBCLK rising 10 ns
t
DLH
AUXLRCLK hold From AUXBCLK rising 5 ns
AD1928
Rev. B | Page 8 of 32
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 8.
Parameter Rating
Analog (AVDD) −0.3 V to +3.6 V
Digital (DVDD) −0.3 V to +3.6 V
Input Current (Except Supply Pins) ±20 mA
Analog Input Voltage (Signal Pins) –0.3 V to AVDD + 0.3 V
Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V
Operating Temperature Range (Case) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
θ
JA
represents thermal resistance, junction-to-ambient;
θ
JC
represents the thermal resistance, junction-to-case. All
characteristics are for a 4-layer board.
Table 9. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
48-Lead LQFP 50.1 17 °C/W
ESD CAUTION
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

AD1928YSTZ

Mfr. #:
Buy AD1928YSTZ
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs 2-8-Audio codec w/on chip PLL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet