AD1928
Rev. B | Page 30 of 32
APPLICATION CIRCUITS
Typical applications circuits are shown in Figure 29 through
Figure 32. Figure 29 shows a typical ADC input filter circuit.
Recommended loop filters for LR clock and master clock as the
PLL reference are shown in Figure 30. Output filters for the
DAC outputs are shown in Figure 31 and Figure 32 for the
noninverting and inverting cases.
2
1
3
OP275
–
+
6
7
5
OP275
–
+
5.76kΩ
5.76kΩ 237Ω
5.76kΩ
120p
600Z
UDI
INPUT
100pF
5.76kΩ
120pF
4.7µF
+
237Ω
4.7µF
+
100pF
1nF
NP0
1nF
NP0
ADCxN
ADCxP
6623-029
Figure 29. Typical ADC Input Filter Circuit
39nF
+
2.2nF
LF
LRCLK
VDD2
3.32kΩ
5.6nF
390pF
LF
MCLK
AVDD2
562Ω
06623-030
Figure 30. Recommended Loop Filters for LRCLK and MCLK PLL Reference
3
1
2
OP275
+
–
4.75kΩ4.75kΩ
4.7µF
+
DAC OUT
240pF
NP0
270pF
NP0
3.3nF
NP0
AUDIO
OUTPUT
4.99kΩ
604Ω
4.99kΩ
49.9kΩ
06623-031
Figure 31. Typical DAC Output Filter Circuit (Single-Ended, Noninverting)
2
1
3
OP275
–
+
3.01kΩ11kΩ
4.7µF
+
DAC
OUT
CM
0.1µF
270pF
NP0
68pF
NP0
2.2nF
NP0
AUDIO
OUTPUT
604Ω
49.9kΩ
11kΩ
06623-032
Figure 32. Typical DAC Output Filter Circuit (Single-Ended, Inverting)
