10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
07/11/05
ISSI
®
IS43R16800A
FUNCTIONAL DESCRIPTION
The 128Mbit DDR SDRAM is a high-speed CMOS
device with four banks that operate at 2.6V. Each
32Mbit bank is organized as 4,096 rows of 512 columns
for the x16 option. Pre-fetch architecture allows Read
and Write accesses to be double-data rate and burst
oriented. Accesses start at a selected column location
and continue every half-clock cycle for a programmed
number of times. The Read or Write operation begins
with an Active command to transmit the selected bank
and row (A0-A11 bits are sampled). This is followed by
a Read or Write command to sample the address bits
again to determine the first column to access. When
access to the memory is not necessary, the device can
be put into a Power Down mode in which current
consumption is minimized. Prior to normal operation,
the device must be initialized in a defined procedure to
function properly. The following sections describe the
steps of initialization, the mode register definitions,
command descriptions, and device operation.
INITIALIZATION
The DDR SDRAM must be powered-on and initialized in
a series of defined steps for proper operation. First,
power is applied to VDD, and then to VDDQ. After
these have reached stable values, VREF and VTT are
ramped up. If this sequence is not followed, latch-up
could occur and cause damage to the device. The
input CKE must be asserted and held to a LVCMOS
Low level during this time to prevent unwanted com-
mands from being executed. The outputs I/O and DQS
remain in high impedance until driven during a normal
operation. Once VDD, VDDQ, VTT, VREF, and CKE are
stable values, the clock inputs can begin to be applied.
For a time period of at least 200µs, valid CLK and CLK
cycles must be applied prior to any command being
issued to the device. CKE needs to then be raised to
SSTL 2 logic High and issue a NOP or Deselect
command to initialize the internal logic of the DRAM.
Next, a Pre-charge All command is given to the device,
followed by a NOP/Deselect command on each clock
cycle for at least tRP. The Load Extended Mode
Register should be issued to enable DLL, followed by
another series of NOP/Deselect commands for at least
tMRD. After this time, the Load Mode Register com-
mand should be issued to reset the DLL, again followed
by a series of NOP or Deselect commands for at least
tMRD. (Note: whenever the DLL is reset, 200 clock
cycles must occur prior to any Read command.) The
Pre-charge command is then issued, with NOP/
Deselect commands for at least tRP. Next, two Auto-
Refresh commands are issued, each followed by NOP/
Deselect commands for at least tRFC. At this point,
the JEDEC specification recommends that a DDR
SDRAM receive another Load Mode Register command
to clear the DLL, with NOP/Deselect commands for at
least tMRD. The device is now ready to receive a valid
command for normal operation.
POWER-UP SEQUENCE AFTER CKE GOES HIGH
