34
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
07/11/05
ISSI
®
IS43R16800A
in0 in1
in2 in3
out0 out1
out2 out3
CK
/CK
DM
DQ
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
BL = 4
CL = 3
DQS
CL=3
Data masked
2 cycle
READ NOPNOPWRIT
High-Z
High-Z
[WRITE to READ delay = 2 clock cycle]
in0 in1
in2
in3
out0 out1
out2 out3
CK
/CK
DM
DQ
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
BL = 4
CL = 3
DQS
Data masked
3 cycle
READWRIT NOP NOP
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
tWTR*
CL=3
[WRITE to READ delay = 3 clock cycle]
Integrated Silicon Solution, Inc. — 1-800-379-4774
35
Rev. 00A
07/11/05
ISSI
®
IS43R16800A
A Read command to the consecutive Precharge command interval (same bank): To output all data
To complete a burst read operation and get a burst length of data, the consecutive precharge command must be
issued tRPD (= BL/ 2 cycles) after the read command is issued.
out0 out1 out2 out3
CK
/CK
DQ
DQS
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
tRPD = BL/2
READ
NOP NOP NOP
PRE/
PALL
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
READ to PRECHARGE Command Interval (same bank): To stop output data
A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become High-Z tHZP
(= CL) after the precharge command.
out0 out1
CK
/CK
DQ
DQS
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
High-Z
High-Z
tHZP
CL = 3
READ
NOP NOP
PRE/PALL
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 2, 4, 8)
36
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
07/11/05
ISSI
®
IS43R16800A
A Write command to the consecutive Precharge command interval (same bank)
The minimum interval tWPD is necessary between the write command and the precharge command.
in0 in1 in2 in3
CK
/CK
DQ
DM
DQS
Command
t1t0 t2 t3 t4 t5 t6 t7
Last data input
tWPD
WRIT NOP
tWR
PRE/PALL
NOP
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
Precharge Termination in Write Cycles
During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command
of the same bank. In order to write the last input data, tWR (min) must be satisfied. When the precharge command
is issued, the invalid data must be masked by DM.
in2 in3
in0 in1
CK
/CK
DQ
DM
DQS
Command
t1t0 t2 t3 t4 t5 t6 t7
Data masked
WRIT NOP NOP
tWR
PRE/PALL
Precharge Termination in Write Cycles (same bank) (BL = 4)

IS43R16800A-5TL-TR

Mfr. #:
Manufacturer:
ISSI
Description:
DRAM 128M 2.5v 8Mx16 400MHz
Lifecycle:
New from this manufacturer.
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