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IS43R16800A-5TL-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. 00A
07/11/05
ISSI
®
IS43R16800A
AC ELECTRICAL CHARACTERISTICS (V
DD
= 2.6V +/- 0.1V, T
A
= 0
o
C to +70
o
C)
-5 (3-4-4)
Symbol Parameter Test Condition Min. Max. Unit
tCK Clock Cycle Time CL = 3 5 10 ns
tCH Clock High Level Width 0.45 0.55 tCK
tCL Clock Low Level Width 0.45 0.55 tCK
tHP Clock Half Period tCH or tCL —ns
tAC Output Access Time from CLK, CLK -0.7 0.7 ns
tDQSCK DQS-Out Access Time from CLK, CLK -0.55 0.55 ns
tDQSQ DQS-DQ Skew — 0.4 ns
tQH Output DQS Valid Window tHP - tQHS —ns
tQHS Data Hold Skew factor — 0.5 ns
tHZ Data Out High Impedance time from CLK, CLK — 0.7 ns
tLZ Data Out Low Impedance time from CLK, CLK -0.7 0.7 ns
tRPRE Read Preamble 0.9 1.1 tCK
tRPST Read Postamble 0.4 0.6 tCK
tDQSS CLK to Valid DQS-In 0.72 1.28 tCK
tDSS DQS falling edge to CK setup time 0.2 — tCK
tDSH DQS falling edge hold time from CLK 0.2 — tCK
tWPRES Write Preamble Setup Time 0 — ns
tWPRE Write Preamble 0.25 — ns
tWPST Write Postamble 0.4 0.6 tCK
tDQSH DQS-In High Level Pulse Width 0.35 — tCK
tDQSL DQS-In Low Level Pulse Width 0.35 — tCK
tIS Address and Control Input Setup Time 0.6 — ns
tIH Address and Control Input Hold Time 0.6 — ns
tIPW Address and Control Input Pulse Width 2.2 — ns
tDS DQ and DM Setup Time to DQS 0.4 — ns
tDH DQ and DM Hold Time to DQS 0.4 — ns
tRC Active to Active/ Auto Refresh Command Period 60 — ns
tRFC Auto Refresh to Active/ Auto Refresh Command Period 70 — ns
tRAS Active to Precharge Command Period 40 120K ns
tRCDRD RAS to CAS Delay in Read 18 — ns
tRCDWR RAS to CAS Delay in Write 18 — ns
tRP Row Pre-charge Time 18 — ns
tRAP Active to Auto Precharge delay tRCD min. — ns
tRRD Row Active to Row Active Delay 10 — ns
tWR Write Recovery Time 15 — ns
tMRD Mode Register Load Delay 2 — tCK
tDAL Auto Pre-charge Write Recovery + Pre-charge
tWR/tCK + tRP/tCK
—tCK
tREF Refresh Interval Time — 15.6 µs
Notes:
1. Operating outside the “Absolute Maximum Ratings” may lead to temporary or permanent device failure.
2. Power up sequence describe in “Initialization” section.
3. All voltages are referenced to Vss.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
07/11/05
ISSI
®
IS43R16800A
Notes:
1. All AC parameters measuremed with the following test conditions.
2. This parameter defines the signal transition delay from the crossing point of CK and CK. The signal transition is defined to occur
when the signal level crosses VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal
transition is defined to occur when the signal level crosses VTT.
5. t
HZ is defined as the data output transition delay from Low-Z to High-Z at the end of a read burst operation. The timing reference
is the crossing point of CK and CK. This parameter is not referred to a specific voltage level, but when the device output stops
driving.
6. t
LZ is defined as the data output transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is referring
to a specific voltage level, but when the device output begins driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal
transition is defined to occur when the signal level crosses V
REF.
8. The timing reference level is V
REF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. There is no specific reference voltage
to judge this transition.
10. t
CK (max.) is determined by the locking range of the DLL. Beyond this lock range, the DLL operation is assured.
11. t
CK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tCK.
12. VDD is assumed to be 2.6V ± 0.1V. VDD power supply variation per cycle expected to be less than 0.4V per 400 cycles.
13. t
DAL = (tWR/tCK)+(tRP/tCK). For each of the add-ins, if not an integer already, round up to the nearest integer.
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. 00A
07/11/05
ISSI
®
IS43R16800A
AC TEST CONDITIONS
Output Load
AC TEST CONDITIONS
Parameter Symbol Value Unit
Input High Voltage VIH (AC) VREF + 0.31 V
Input Low Voltage VIL (AC) VREF - 0.31 V
Input Signal Slew Rate SLEW 1 V/ns
Input Timing Reference Level VREF VDDQ/2 V
Termination Voltage VTT VREF V
Input Differential Voltage (CLK and CLK)VID (AC) 0.62 V
Input Differential Crossing Voltage VIX (AC) VREF V
DQ
R
T
= 50 Ω
V
TT
CL = 30 pF
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER UNITS
tWPD Write to Pre-charge command delay (same bank) 4 + BL/2 Cycle
tRPD Read to Pre-charge command delay (same bank) BL/2 Cycle
tWRD Write to Read command delay (to input all data) 2 + BL/2 Cycle
tBSTW Burst Stop command to Write command delay 3 Cycle
tBSTZ Burst Stop command to DQ High-Z 3 Cycle
tRWD Read command to Write command delay (to output all data) 3 + BL/2 Cycle
tHZP Pre-charge command to High-Z 3 Cycle
tWCD Write command to data in latency 1 Cycle
tWR Write Recovery 3 Cycle
tDMD DM to Data-In latency 0 Cycle
tMRD Mode Register Set command cycle time 2 Cycle
tSNR Self Refresh Exit to non-read command 15 Cycle
tSRD Self Refresh Exit to Read command 200 Cycle
tPDEN Power Down Entry 1 Cycle
tPDEX Power Down Exit to command input 1 Cycle
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

IS43R16800A-5TL-TR

Mfr. #:
Buy IS43R16800A-5TL-TR
Manufacturer:
ISSI
Description:
DRAM 128M 2.5v 8Mx16 400MHz
Lifecycle:
New from this manufacturer.
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