AD7730BRUZ Datasheet AD7730BRUZ, AD7730BNZ, AD7730BRZ | P10-P12

AD7730/AD7730L

–10–

OUTPUT NOISE AND RESOLUTION SPECIFICATION

The AD7730 can be programmed to operate in either chop mode or nonchop mode. The chop mode can be enabled in ac-excited or

dc-excited applications; it is optional in dc-excited applications, but chop mode must be enabled in ac-excited applications. These

options are discussed in more detail in later sections. The chop mode has the advantage of lower drift numbers and better noise im-

munity, but the noise is approximately 20% higher for a given –3 dB frequency and output data rate. It is envisaged that the majority

of weigh-scale users of the AD7730 will operate the part in chop mode to avail themselves of the excellent drift performance and

noise immunity when chopping is enabled. The following tables outline the noise performance of the part in both chop and nonchop

modes over all input ranges for a selection of output rates. Settling time refers to the time taken to get an output that is 100% settled

to new value.

Output Noise (CHP = 1)

This mode is the primary mode of operation of the device. Table I shows the output rms noise for some typical output update rates

and –3 dB frequencies for the AD7730 when used in chopping mode (CHP of Filter Register = 1) with a master clock frequency of

4.9152 MHz. These numbers are typical and are generated at a differential analog input voltage of 0 V. The output update rate is

selected via the SF0 to SF11 bits of the Filter Register. Table II, meanwhile, shows the output peak-to-peak resolution in counts for

the same output update rates. The numbers in brackets are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5

LSB). It is important to note that the numbers in Table II represent the resolution for which there will be no code flicker within a

six-sigma limit. They are not calculated based on rms noise, but on peak-to-peak noise.

The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the

same as the equivalent bipolar input range. As a result, the numbers in Table I will remain the same for unipolar ranges while the

numbers in Table II will change. To calculate the numbers for Table II for unipolar input ranges simply divide the peak-to-peak

resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits.

Table I. Output Noise vs. Input Range and Update Rate (CHP = 1)

Typical Output RMS Noise in nV

Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range

Data Rate Frequency Word Normal Mode Fast Mode = 80 mV = 40 mV = 20 mV = 10 mV

50 Hz 1.97 Hz 2048 460 ms 60 ms 115 75 55 40

100 Hz 3.95 Hz 1024 230 ms 30 ms 155 105 75 60

150 Hz 5.92 Hz 683 153 ms 20 ms 200 135 95 70

200 Hz* 7.9 Hz 512 115 ms 15 ms 225 145 100 80

400 Hz 15.8 Hz 256 57.5 ms 7.5 ms 335 225 160 110

*Power-On Default

Table II. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1)

Peak-to-Peak Resolution in Counts (Bits)

Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range

Data Rate Frequency Word Normal Mode Fast Mode = 80 mV = 40 mV = 20 mV = 10 mV

50 Hz 1.97 Hz 2048 460 ms 60 ms 230k (18) 175k (17.5) 120k (17) 80k (16.5)

100 Hz 3.95 Hz 1024 230 ms 30 ms 170k (17.5) 125k (17) 90k (16.5) 55k (16)

150 Hz 5.92 Hz 683 153 ms 20 ms 130k (17) 100k (16.5) 70k (16) 45k (15.5)

200 Hz* 7.9 Hz 512 115 ms 15 ms 120k (17) 90k (16.5) 65k (16) 40k (15.5)

400 Hz 15.8 Hz 256 57.5 ms 7.5 ms 80k (16.5) 55k (16) 40k (15.5) 30k (15)

*Power-On Default

Output Noise (CHP = 0)

Table III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7730 when used in non-

chopping mode (CHP of Filter Register = 0) with a master clock frequency of 4.9152 MHz. These numbers are typical and are gen-

erated at a differential analog input voltage of 0 V. The output update rate is selected via the SF0 to SF11 bits of the Filter Register.

Table IV, meanwhile, shows the output peak-to-peak resolution in counts for the same output update rates. The numbers in brackets

are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB). It is important to note that the numbers in Table

IV represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on rms

noise, but on peak-to-peak noise.

The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the

same as the equivalent bipolar input range. As a result, the numbers in Table III will remain the same for unipolar ranges while the

numbers in Table IV will change. To calculate the number for Table IV for unipolar input ranges simply divide the peak-to-peak

resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits.

REV. B

AD7730/AD7730L

–11–

Table III. Output Noise vs. Input Range and Update Rate (CHP = 0)

Typical Output RMS Noise in nV

Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range

Data Rate Frequency Word Normal Mode Fast Mode = 80 mV = 40 mV = 20 mV = 10 mV

150 Hz 5.85 Hz 2048 166 ms 26.6 ms 160 110 80 60

200 Hz 7.8 Hz 1536 125 ms 20 ms 190 130 95 75

300 Hz 11.7 Hz 1024 83.3 ms 13.3 ms 235 145 100 80

600 Hz 23.4 Hz 512 41.6 ms 6.6 ms 300 225 135 110

1200 Hz 46.8 Hz 256 20.8 ms 3.3 ms 435 315 210 150

Table IV. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 0)

Peak-to-Peak Resolution in Counts (Bits)

Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range

Data Rate Frequency Word Normal Mode Fast Mode = 80 mV = 40 mV = 20 mV = 10 mV

150 Hz 5.85 Hz 2048 166 ms 26.6 ms 165k (17.5) 120k (17) 80k (16.5) 55k (16)

200 Hz 7.8 Hz 1536 125 ms 20 ms 140k (17) 100k (16.5) 70k (16) 45k (15.5)

300 Hz 11.7 Hz 1024 83.3 ms 13.3 ms 115k (17) 90k (16.5) 65k (16) 40k (15.5)

600 Hz 23.4 Hz 512 41.6 ms 6.6 ms 90k (16.5) 60k (16) 50k (15.5) 30k (15)

1200 Hz 46.8 Hz 256 20.8 ms 3.3 ms 60k (16) 43k (15.5) 32k (15) 20k (14.5)

ON-CHIP REGISTERS

The AD7730 contains thirteen on-chip registers which can be accessed via the serial port of the part. These registers are summarized

in Figure 4 and in Table V and described in detail in the following sections.

COMMUNICATIONS REGISTER

STATUS REGISTER

DATA REGISTER

MODE REGISTER

FILTER REGISTER

DAC REGISTER

OFFSET REGISTER (x3)

GAIN REGISTER (x3)

TEST REGISTER

RS2 RS1 RS0

DIN

DOUT

DIN

DOUT

SELECT

DECODER

Figure 4. Register Overview

REV. B

AD7730/AD7730L

–12–

Table V. Summary of On-Chip Registers

Power-On/Reset

Communications Write Only 8 Bits Not Applicable All operations to other registers are initiated through

subsequent operations are read or write operations

and also selects the register for that subsequent

operation. Most subsequent operations return con-

trol to the Communications Register except for the

continuous read mode of operation.

Status Register Read Only 8 Bits CX Hex Provides status information on conversions, calibra-

tions, settling to step inputs, standby operation and

the validity of the reference voltage.

Data Register Read Only 16 Bits or 24 Bits 000000 Hex Provides the most up-to-date conversion result from

the part. Register length can be programmed to be

16 bits or 24 bits.

Mode Register Read/Write 16 Bits 01B0 Hex Controls functions such as mode of operation, uni-

polar/bipolar operation, controlling the function of

AIN2(+)/D1 and AIN2(-)/D0, burnout current,

Data Register word length and disabling of MCLK

OUT. It also contains the reference selection bit, the

range selection bits and the channel selection bits.

Filter Register Read/Write 24 Bits 200010 Hex Controls the amount of averaging in the first stage

filter, selects the fast step and skip modes and con-

trols the ac excitation and chopping modes on the

part.

DAC Register Read/Write 8 Bits 20 Hex Provides control of the amount of correction per-

formed by the Offset/TARE DAC.

Offset Register Read/Write 24 Bits 800000 Hex Contains a 24-bit word which is the offset calibration

coefficient for the part. The contents of this register

are used to provide offset correction on the output

from the digital filter. There are three Offset Regis-

ters on the part and these are associated with the

input channels as outlined in Table XIII.

Gain Register Read/Write 24 Bits 59AEE7 Hex Contains a 24-bit word which is the gain calibration

coefficient for the part. The contents of this register

are used to provide gain correction on the output

from the digital filter. There are three Gain Registers

on the part and these are associated with the input

channels as outlined in Table XIII.

Test Register Read/Write 24 Bits 000000 Hex Controls the test modes of the part which are used

when testing the part. The user is advised not to

change the contents of this register.

WEN ZERO RW1 RW0 ZERO RS2 RS1 RS0

RDY STDY STBY NOREF MS3 MS2 MS1 MS0

MD2 MD1 MD0 B/U DEN D1 D0 WL

HIREF ZERO RN1 RN0 CLKDIS BO CH1 CH0

SF11 SF10 SF9 SF8 SF7 SF6 SF5 SF4

SF3 SF2 SF1 SF0 ZERO ZERO SKIP FAST

ZERO ZERO AC CHP DL3 DL2 DL1 DL0

ZERO ZERO DAC5 DAC4 DAC3 DAC2 DAC1 DAC0

REV. B

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P53

AD7730BRUZ

Mfr. #:

Buy AD7730BRUZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC CMOS 24-Bit Bridge Transducer

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AD7730BRUZ

AD7730BRUZ

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