AD7730BRUZ Datasheet AD7730BRUZ, AD7730BNZ, AD7730BRZ | P22-P24

AD7730/AD7730L

–22–

CALIBRATION OPERATION SUMMARY

The AD7730 contains a number of calibration options as outlined previously. Table XVII summarizes the calibration types, the

operations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to

monitor the hardware RDY pin using either interrupt-driven or polling routines. The second method is to do a software poll of the

RDY bit in the Status Register. This can be achieved by setting up the part for continuous reads of the Status Register once a calibra-

tion has been initiated. The RDY pin and RDY bit go high on initiating a calibration and return low at the end of the calibration

routine. At this time, the MD2, MD1, MD0 bits of the Mode Register have returned to 0, 0, 0. The FAST and SKIP bits are treated

as 0 for the calibration sequence so the full filter is always used for the calibration routines. See Calibration section for full detail.

Table XVII. Calibration Operations

MD2, MD1, Duration to RDY Duration to RDY

Calibration Type MD0 Low (CHP = 1) Low (CHP = 0) Calibration Sequence

Internal Zero-Scale 1, 0, 0 22 × 1/Output Rate 24 × 1/Output Rate Calibration on internal shorted input with PGA set for

selected input range. The ac bit is ignored for this calibra-

tion sequence. The sequence is performed with dc excitation.

The Offset Calibration Register for the selected channel is

updated at the end of this calibration sequence. For full self-

calibration, this calibration should be preceded by an Internal

Full-Scale calibration. For applications which require an

Internal Zero-Scale and System Full-Scale calibration, this

Internal Zero-Scale calibration should be performed first.

Internal Full-Scale 1, 0, 1 44 × 1/Output Rate 48 × 1/Output Rate Calibration on internally-generated input full-scale with

PGA set for selected input range. The ac bit is ignored for

this calibration sequence. The sequence is performed with

dc excitation. The Gain Calibration Register for the

selected channel is updated at the end of this calibration

sequence. It is recommended that internal full-scale

calibrations are performed on the 80 mV range, regardless

of the subsequent operating range, to optimize the post-

calibration gain error. This calibration should be followed

by either an Internal Zero-Scale or System Zero-Scale

calibration. This zero-scale calibration should be

performed at the operating input range.

System Zero-Scale 1, 1, 0 22 × 1/Output Rate 24 × 1/Output Rate Calibration on externally applied input voltage with PGA

set for selected input range. The input applied is assumed

to be the zero scale of the system. If ac = 1, the system

continues to use ac excitation for the duration of the

calibration. For full system calibration, this System Zero-

Scale calibration should be performed first. For applications

which require a System Zero-Scale and Internal Full-Scale

calibration, this calibration should be preceded by the

Internal Full-Scale calibration. The Offset Calibration

this calibration sequence.

System Full-Scale 1, 1, 1 22 × 1/Output Rate 24 × 1/Output Rate Calibration on externally-applied input voltage with PGA

set for selected input range. The input applied is assumed

to be the full-scale of the system. If ac = 1, the system

continues to use ac excitation for the duration of the

calibration. This calibration should be preceded by a

System Zero-Scale or Internal Zero-Scale calibration. The

Gain Calibration Register for the selected channel is

updated at the end of this calibration sequence.

REV. B

AD7730/AD7730L

–23–

CIRCUIT DESCRIPTION

The AD7730 is a sigma-delta A/D converter with on-chip digital

filtering, intended for the measurement of wide dynamic range,

low-frequency signals such as those in weigh-scale, strain-gage,

pressure transducer or temperature measurement applications.

It contains a sigma-delta (or charge-balancing) ADC, a calibra-

tion microcontroller with on-chip static RAM, a clock oscillator,

a digital filter and a bidirectional serial communications port.

The part consumes 13 mA of power supply current with a standby

mode which consumes only 25 μA. The part operates from a single

+5 V supply. The clock source for the part can be provided via an

external clock or by connecting a crystal oscillator or ceramic

resonator across the MCLK IN and MCLK OUT pins.

The part contains two programmable-gain fully differential analog

input channels. The part handles a total of eight different input

ranges which are programmed via the on-chip registers. There are

four differential unipolar ranges: 0 mV to +10 mV, 0 mV to

+20 mV, 0 mV to +40 mV and 0 mV to +80 mV and four differen-

tial bipolar ranges: ±10 mV, ± 20 mV, ± 40 mV and ±80 mV.

The AD7730 employs a sigma-delta conversion technique to

realize up to 24 bits of no missing codes performance. The

sigma-delta modulator converts the sampled input signal into a

digital pulse train whose duty cycle contains the digital informa-

tion. A digital low-pass filter processes the output of the sigma-

delta modulator and updates the data register at a rate that can

be programmed over the serial interface. The output data from

the part is accessed over this serial interface. The cutoff frequency

and output rate of this filter can be programmed via on-chip

registers. The output noise performance and peak-to-peak reso-

lution of the part varies with gain and with the output rate as

shown in Tables I to IV.

The analog inputs are buffered on-chip allowing the part to

handle significant source impedances on the analog input. This

means that external R, C filtering (for noise rejection or RFI

reduction) can be placed on the analog inputs if required. Both

analog channels are differential, with a common-mode voltage

range that comes within 1.2 V of AGND and 0.95 V of AV

The reference input is also differential and the common-mode

range here is from AGND to AV

The part contains a 6-bit DAC that is controlled via on-chip

registers. This DAC can be used to remove TARE values of up

to ± 80 mV from the analog input signal range. The resolution

on this TARE function is 1.25 mV for a +2.5 V reference and

2.5 mV with a +5 V reference.

The AD7730 can accept input signals from a dc-excited bridge.

It can also handle input signals from an ac-excited bridge by

using the ac excitation clock signals (ACX and ACX) to switch

the supplies to the bridge. ACX and ACX are nonoverlapping

clock signals used to synchronize the external ac supplies that

drive the transducer bridge. These ACX clocks are demodulated

on the AD7730 input.

The AD7730 contains a number of hardware and software

events that set or reset status flags and bits in registers. Table

XVIII summarizes which blocks and flags are affected by the

different events.

Table XVIII. Reset Events

Set Registers Mode Filter Analog Reset Serial Set RDY Set STDY

Event to Default Bits Reset Power-Down Interface Pin/Bit Bit

Power-On Reset Yes 000 Yes Yes Yes Yes Yes

RESET Pin Yes 000 Yes No Yes Yes Yes

STANDBY Pin No As Is Yes Yes No Yes Yes

Mode 011 Write No 011 Yes Yes No Yes Yes

SYNC Pin No As Is Yes No No Yes Yes

Mode 000 Write No 000 Yes No No Yes Yes

Conversion or No New Initial No No Yes Yes

Cal Mode Write Value Reset

Clock 32 1s Yes 000 Yes No Yes Yes Yes

Data Register Read No As Is No No No Yes No

REV. B

AD7730/AD7730L

–24–

ANALOG INPUT

Analog Input Channels

The AD7730 contains two differential analog input channels, a

primary input channel, AIN1, and a secondary input channel,

AIN2. The input pairs provide programmable gain, differential

channels which can handle either unipolar or bipolar input

signals. It should be noted that the bipolar input signals are

referenced to the respective AIN(–) input of the input pair. The

secondary input channel can also be reconfigured as two digital

output port bits.

A two-channel differential multiplexer switches one of the two

input channels to the on-chip buffer amplifier. This multiplexer

is controlled by the CH0 and CH1 bits of the Mode Register.

When the analog input channel is switched, the RDY output

goes high and the settling time of the part must elapse before a

valid word from the new channel is available in the Data Regis-

ter (indicated by RDY going low).

Buffered Inputs

The output of the multiplexer feeds into a high impedance input

stage of the buffer amplifier. As a result, the analog inputs can

handle significant source impedances. This buffer amplifier has

an input bias current of 50 nA (CHP = 1) and 60 nA (CHP = 0).

This current flows in each leg of the analog input pair. The

offset current on the part is the difference between the input

bias on the legs of the input pair. This offset current is less than

10 nA (CHP = 1) and 30 nA (CHP = 0). Large source resis-

tances result in a dc offset voltage developed across the source

resistance on each leg, but matched impedances on the analog

input legs will reduce the offset voltage to that generated by the

input offset current.

Analog Input Ranges

The absolute input voltage range is restricted to between

AGND + 1.2 V to AV

– 0.95 V, which also places restrictions

on the common-mode range. Care must be taken in setting up

the common-mode voltage and input voltage range so these

limits are not exceeded, otherwise there will be a degradation in

linearity performance.

In some applications, the analog input range may be biased

either around system ground or slightly below system ground. In

such cases, the AGND of the AD7730 must be biased negative

with respect to system ground so the analog input voltage does

not go within 1.2 V of AGND. Care should taken to ensure that

the differential between either AV

or DV

and this biased

AGND does not exceed 5.5 V. This is discussed in more detail

in the Applications section.

Programmable Gain Amplifier

The output from the buffer amplifier is summed with the output

of the 6-bit Offset DAC before it is applied to the input of the

on-chip programmable gain amplifier (PGA). The PGA can

handle four different unipolar input ranges and four bipolar

ranges. With the HIREF bit of the Mode Register at 0 and a

+2.5 V reference (or the HIREF bit at 1 and a +5 V reference),

the unipolar ranges are 0 mV to +10 mV, 0 mV to +20 mV,

0 mV to +40 mV, and 0 mV to +80 mV, while the bipolar ranges

are ± 10 mV, ± 20 mV, ± 40 mV and ± 80 mV. These are the

nominal ranges that should appear at the input to the on-chip

PGA.

Offset DAC

The purpose of the Offset DAC is to either add or subtract an

offset so the input range at the input to the PGA is as close as

possible to the nominal. If the output of the 6-bit Offset DAC is

0 V, the differential voltage ranges that appear at the analog

input to the part will also appear at the input to the PGA. If,

however, the Offset DAC has an output voltage other than 0 V,

the input range to the analog inputs will differ from that applied

to the input of the PGA.

The Offset DAC has five magnitude bits and one sign bit. The

sign bit determines whether the value loaded to the five magni-

tude bits is added to or subtracted from the voltage at the ana-

log input pins. Control of the Offset DAC is via the DAC

section. With a 5 V reference applied between the REF IN pins,

the resolution of the Offset DAC is 2.5 mV with a range that

allows addition or subtraction of 77.5 mV. With a 2.5 V refer-

ence applied between the REF IN pins, the resolution of the

Offset DAC is 1.25 mV with a range that allows addition or

subtraction of 38.75 mV.

Following is an example of how the Offset DAC works. If the

differential input voltage range the user had at the analog input

pins was +20 mV to +30 mV, the Offset DAC should be pro-

grammed to subtract 20 mV of offset so the input range to the

PGA is 0 mV to +10 mV. If the differential input voltage range

the user had at the analog input pins was –60 mV to +20 mV,

the Offset DAC should be programmed to add 20 mV of offset so

the input range to the PGA is ± 40 mV.

Bipolar/Unipolar Inputs

The analog inputs on the AD7730 can accept either unipolar or

bipolar input voltage ranges. Bipolar input ranges do not imply

that the part can handle negative voltages with respect to system

ground on its analog inputs unless the AGND of the part is also

biased below system ground. Unipolar and bipolar signals on

the AIN(+) input are referenced to the voltage on the respective

AIN(–) input. For example, if AIN(–) is +2.5 V and the AD7730 is

configured for an analog input range of 0 to +10 mV with no

DAC offset correction, the input voltage range on the AIN(+)

input is +2.5 V to +2.51 V. Similarly, if AIN(–) is +2.5 V and the

AD7730 is configured for an analog input range of ±80 mV

with no DAC offset correction, the analog input range on the

AIN(+) input is +2.42 V to +2.58 V (i.e., 2.5 V ± 80 mV).

Bipolar or unipolar options are chosen by programming the B/U

bit of the Mode Register. This programs the selected channel

for either unipolar or bipolar operation. Programming the chan-

nel for either unipolar or bipolar operation does not change any

of the input signal conditioning; it simply changes the data

output coding and the points on the transfer function where

calibrations occur. When the AD7730 is configured for unipolar

operation, the output coding is natural (straight) binary with a

zero differential voltage resulting in a code of 000 . . . 000, a

midscale voltage resulting in a code of 100 . . . 000 and a full-

scale input voltage resulting in a code of 111 . . . 111. When the

AD7730 is configured for bipolar operation, the coding is offset

binary with a negative full scale voltage resulting in a code of

000 . . . 000, a zero differential voltage resulting in a code of

100 . . . 000 and a positive full scale voltage resulting in a code

of 111 . . . 111.

REV. B

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P53

AD7730BRUZ

Mfr. #:

Buy AD7730BRUZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC CMOS 24-Bit Bridge Transducer

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD7730BRUZ

AD7730BRUZ

Products related to this Datasheet