AD7730BRUZ Datasheet AD7730BRUZ, AD7730BNZ, AD7730BRZ | P28-P30

AD7730/AD7730L

–28–

Because of this effect, care should be taken in choosing an out-

put rate that is close to the line frequency in the application. If

the line frequency is 50 Hz, an output update rate of 50 Hz

should not be chosen as it will significantly reduce the AD7730’s

line frequency rejection (the 50 Hz will appear as a dc effect

with only 6 dB attenuation). Choosing an output rate of 55 Hz

will result in a 6 dB—attenuated aliased frequency of 5 Hz with

only a further 25 dB attenuation based on the filter profile. This

number is based on the filter roll-off and Figure 11 can be used

as a reference by dividing the frequency scale by a factor of 4.

Choosing 57 Hz as the output rate will give better than 90 dB

attenuation of the aliased line frequency which appears as a

7 Hz signal. Similarly, multiples of the line frequency should be

avoided as the output rate because harmonics of the line fre-

quency will not be fully attenuated. The programmability of the

AD7730’s output rate should allow the user to readily choose an

output rate that overcomes this issue. An alternative is to use

the part in nonchop mode.

Figure 13 shows the frequency response for the AD7730 with

the second stage filter set for normal FIR operation, chop mode

disabled, the decimal equivalent of the word in the SF bits set to

1536 and a master clock frequency of 4.9152 MHz. The response

is analogous to that of Figure 11, with the three-times-larger SF

word producing the same 200 Hz output rate. Once again, the

response will scale proportionally with master clock frequency.

The response is shown from dc to 100 Hz. The rejection at

50 Hz ± 1 Hz, and 60 Hz ± 1 Hz is better than 88 dB.

FREQUENCY – Hz

–60

–100

090

GAIN – dB

10 20 30 40 50 60 70 80

–10

–50

–70

–90

–30

–40

–80

–20

–120

–110

100

Figure 13. Detailed Full Frequency Response of AD7730

(Second Stage Filter as Normal FIR, Chop Disabled)

The –3 dB frequency for the frequency response of the AD7730

with the second stage filter set for normal FIR operation and

chop mode enabled, is determined by the following relationship:

3dB

= 0.039 ×

CLK IN

In this case, f

3 dB

= 7.8 Hz and the stop band, where the attentua-

tion is greater than 64.5 dB, is determined by:

STOP

= 0.14 ×

CLK IN

In this case, f

3 dB

= 28 Hz.

Figure 14 shows the frequency response for the same set of

conditions as for Figure 13, but in this case the response is

shown out to 600 Hz. This plot is comparable to that of Figure

12. The most notable difference is the absence of the peaks in

the response at 200 Hz and 400 Hz. As a result, interference at

these frequencies will be effectively eliminated before being

aliased back to dc.

FREQUENCY – Hz

–60

–100

0450

GAIN – dB

50 100 150 200 250 300 350 400

–10

–50

–70

–90

–30

–40

–80

–20

–120

–110

500 550 600

Figure 14. Expanded Full Frequency Response of AD7730

(Second Stage Filter as Normal FIR, Chop Disabled)

REV. B

AD7730/AD7730L

–29–

FASTStep Mode

The second mode of operation of the second stage filter is in

FASTStep

mode which enables it to respond rapidly to step

inputs. This

FASTStep

mode is enabled by placing a 1 in the

FAST bit of the Filter Register. If the FAST bit is 0, the part

continues to process step inputs with the normal FIR filter as

the second stage filter. With

FASTStep

mode enabled, the

second stage filter will continue to process steady state inputs

with the filter in its normal FIR mode of operation. However,

the part is continuously monitoring the output of the first stage

filter and comparing it with the second previous output. If the

difference between these two outputs is greater than a predeter-

mined threshold (1% of full scale), the second stage filter switches

to a simple moving average computation. When the step change

is detected, the STDY bit of the Status Register goes to 1 and

will not return to 0 until the FIR filter is back in the processing

loop.

The initial number of averages in the moving average computa-

tion is either 2 (chop enabled) or 1 (chop disabled). The num-

ber of averages will be held at this value as long as the threshold

is exceeded. Once the threshold is no longer exceeded (the step

on the analog input has settled), the number of outputs used to

compute the moving average output is increased. The first and

second outputs from the first stage filter where the threshold is

no longer exceeded is computed as an average by two, then four

outputs with an average of four, eight outputs with an average of

eight, and six outputs with an average of 16. At this time, the

second stage filter reverts back to its normal FIR mode of opera-

tion. When the second stage filter reverts back to the normal FIR,

the STDY bit of the Status Register goes to 0.

Figure 15 shows the different responses to a step input with

FASTStep

mode enabled and disabled. The vertical axis shows

the code value returned by the AD7730 and indicates the set-

tling of the output to the input step change. The horizontal axis

shows the number of outputs it takes for that settling to occur.

The positive input step change occurs at the fifth output. In

FASTStep

mode, the output has settled to the final value by the

eighth output. In normal mode, the output has not reached

close to its final value until after the 25th output.

NUMBER OF OUTPUTS

20000000

15000000

0255

CODE

10 15 20

10000000

5000000

Figure 15. Step Response for FAST

Step

and Normal

Operation

FASTStep

mode, the part has settled to the new value much

faster. With chopping enabled, the

FASTStep

mode settles to

its value in two outputs, while the normal mode settling takes

23 outputs. Between the second and 23rd output, the

FASTStep

mode produces a settled result, but with additional noise com-

pared to the specified noise level for its operating conditions. It

starts at a noise level that is comparable to SKIP mode and as

the averaging increases ends up at the specified noise level. The

complete settling time to where the part is back within the

specified noise number is the same for

FASTStep

mode and

normal mode. As can be seen from Figure 13, the

FASTStep

mode gives a much earlier indication of where the output chan-

nel is going and its new value. This feature is very useful in

weighing applications to give a much earlier indication of the

weight, or in an application scanning multiple channels where

the user does not have to wait the full settling time to see if a

channel has changed value.

SKIP Mode

The final method for operating the second stage filter is where it

is bypassed completely. This is achieved by placing a 1 in the

SKIP bit of the Filter Register. When SKIP mode is enabled, it

means that the only filtering on the part is the first stage, sinc

filter. As a result, the complete filter profile is as described ear-

lier for the first stage filter and illustrated in Figure 10.

In SKIP mode, because there is much less processing of the data

to derive each individual output, the normal mode settling time

for the part is shorter. As a consequence of the lesser filtering,

however, the output noise from the part will be significantly

higher for a given SF word. For example with a 20 mV, an SF

word of 1536 and CHP = 0, the output rms noise increases

from 80 nV to 200 nV. With a 10 mV input range, an SF word

of 1024 and CHP = 1, the output rms noise goes from 60 nV to

200 nV.

With chopping disabled and SKIP mode enabled, each output

from the AD7730 is a valid result in itself. However, with chop-

ping enabled and SKIP mode enabled, the outputs from the

AD7730 must be handled in pairs as each successive output is

from reverse chopping polarities.

CALIBRATION

The AD7730 provides a number of calibration options which

can be programmed via the MD2, MD1 and MD0 bits of the

Mode Register. The different calibration options are outlined in

the Mode Register and Calibration Operations sections. A cali-

bration cycle may be initiated at any time by writing to these

bits of the Mode Register. Calibration on the AD7730 removes

offset and gain errors from the device.

The AD7730 gives the user access to the on-chip calibration

registers allowing the microprocessor to read the device’s cali-

bration coefficients and also to write its own calibration coeffi-

cients to the part from prestored values in E

PROM. This gives

the microprocessor much greater control over the AD7730’s

calibration procedure. It also means that the user can verify that

the device has performed its calibration correctly by comparing

the coefficients after calibration with prestored values in

PROM. The values in these calibration registers are 24 bits

wide. In addition, the span and offset for the part can be adjusted

by the user.

REV. B

AD7730/AD7730L

–30–

Internally in the AD7730, the coefficients are normalized before

being used to scale the words coming out of the digital filter.

The offset calibration register contains a value which, when

normalized, is subtracted from all conversion results. The gain

calibration register contains a value which, when normalized, is

multiplied by all conversion results. The offset calibration coeffi-

cient is subtracted from the result prior to the multiplication by

the gain coefficient.

The AD7730 offers self-calibration or system calibration facili-

ties. For full calibration to occur on the selected channel, the on-

chip microcontroller must record the modulator output for two

different input conditions. These are “zero-scale” and “full-

scale” points. These points are derived by performing a conver-

sion on the different input voltages provided to the input of the

modulator during calibration. The result of the “zero-scale”

calibration conversion is stored in the Offset Calibration Regis-

ter for the appropriate channel. The result of the “full-scale”

calibration conversion is stored in the Gain Calibration Register

for the appropriate channel. With these readings, the microcon-

troller can calculate the offset and the gain slope for the input to

output transfer function of the converter. Internally, the part

works with 33 bits of resolution to determine its conversion

result of either 16 bits or 24 bits.

The sequence in which the zero-scale and full-scale calibration

occurs depends upon the type of full-scale calibration being

performed. The internal full-scale calibration is a two-step cali-

bration that alters the value of the Offset Calibration Register.

Thus, the user must perform a zero-scale calibration (either

internal or system) after an internal full-scale calibration to correct

the Offset Calibration Register contents. When using system

full-scale calibration, it is recommended that the zero-scale

calibration (either internal or system) is performed first.

Since the calibration coefficients are derived by performing a

conversion on the input voltage provided, the accuracy of the

calibration can only be as good as the noise level the part pro-

vides in normal mode. To optimize the calibration accuracy, it

is recommended to calibrate the part at its lowest output rate

where the noise level is lowest. The coefficients generated at any

output update rate will be valid for all selected output update

rates. This scheme of calibrating at the lowest output update

rate does mean that the duration of calibration is longer.

Internal Zero-Scale Calibration

An internal zero-scale calibration is initiated on the AD7730 by

writing the appropriate values (1, 0, 0) to the MD2, MD1 and

MD0 bits of the Mode Register. In this calibration mode with a

unipolar input range, the zero-scale point used in determining

the calibration coefficients is with the inputs of the differential

pair internally shorted on the part (i.e., AIN(+) = AIN(–) =

Externally-Applied AIN(–) voltage). The PGA is set for the

selected gain (as per the RN1, RN0 bits in the Mode Register)

for this internal zero-scale calibration conversion.

The calibration is performed with dc excitation regardless of the

status of the ac bit. The duration time of the calibration de-

pends upon the CHP bit of the Filter Register. With CHP = 1,

the duration is 22 × 1/Output Rate; with CHP = 0, the duration

is 24 × 1/Output Rate. At this time the MD2, MD1 and MD0

bits in the Mode Register return to 0, 0, 0 (Sync or Idle Mode

for the AD7730). The RDY line goes high when calibration is

initiated and returns low when calibration is complete. Note

that the part has not performed a conversion at this time; it has

simply performed a zero-scale calibration and updated the Off-

set Calibration Register for the selected channel. The user must

write either 0, 0, 1 or 0, 1, 0 to the MD2, MD1, MD0 bits of the

Mode Register to initiate a conversion. If RDY is low before (or

goes low during) the calibration command write to the Mode

before RDY goes high to indicate that calibration is in progress.

Therefore, RDY should be ignored for up to one modulator

cycle after the last bit of the calibration command is written to

the Mode Register.

For bipolar input ranges in the internal zero-scale calibrating

mode, the sequence is very similar to that just outlined. In this

case, the zero-scale point is exactly the same as above but since

the part is configured for bipolar operation, the output code for

zero differential input is 800000 Hex in 24-bit mode.

The internal zero-scale calibration needs to be performed as

one part of a two part full calibration. However, once a full

calibration has been performed, additional internal zero-scale

calibrations can be performed by themselves to adjust the

part’s zero-scale point only. When performing a two step full

calibration care should be taken as to the sequence in which the

two steps are performed. If the internal zero-scale calibration is

one part of a full self-calibration, then it should take place after

an internal full-scale calibration. If it takes place in association

with a system full-scale calibration, then this internal zero-scale

calibration should be performed first.

Internal Full-Scale Calibration

An internal full-scale calibration is initiated on the AD7730 by

writing the appropriate values (1, 0, 1) to the MD2, MD1 and

MD0 bits of the Mode Register. In this calibration mode, the

full-scale point used in determining the calibration coefficients is

with an internally-generated full-scale voltage. This full-scale

voltage is derived from the reference voltage for the AD7730

and the PGA is set for the selected gain (as per the RN1, RN0

bits in the Mode Register) for this internal full-scale calibration

conversion.

In order to meet the post-calibration numbers quoted in the

specifications, it is recommended that internal full-scale calibra-

tions be performed on the 80 mV range. This applies even if the

subsequent operating mode is on the 10 mV, 20 mV or 40 mV

input ranges.

The internal full-scale calibration is a two-step sequence that

runs when an internal full-scale calibration command is written

to the AD7730. One part of the calibration is a zero-scale cali-

bration and as a result, the contents of the Offset Calibration

The user must therefore perform a zero-scale calibration (either

internal or system) AFTER the internal full-scale calibration.

This zero-scale calibration should be performed at the operating input

range.

This means that internal full-scale calibrations cannot be

performed in isolation.

The calibration is performed with dc excitation regardless of the

status of the ac bit. The duration time of the calibration de-

pends upon the CHP bit of the Filter Register. With CHP = 1,

the duration is 44 × 1/Output Rate; with CHP = 0, the duration

is 48 × 1/Output Rate. At this time the MD2, MD1 and MD0

bits in the Mode Register return to 0, 0, 0 (Sync or Idle Mode

for the AD7730). The RDY line goes high when calibration is

initiated and returns low when calibration is complete. Note

that the part has not performed a conversion at this time. The

REV. B

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P53

AD7730BRUZ

Mfr. #:

Buy AD7730BRUZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC CMOS 24-Bit Bridge Transducer

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AD7730BRUZ

AD7730BRUZ

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