AD7730/AD7730L
–4–
NOTES
11
Temperature range: –40°C to +85°C.
12
Sample tested during initial release.
13
The offset (or zero) numbers with CHP = 1 are typically 3 μV precalibration. Internal zero-scale calibration reduces this by about 1 μV. Offset numbers with CHP = 0 can be up to
1 mV precalibration. Internal zero-scale calibration reduces this to 2 μV typical. System zero-scale calibration reduces offset numbers with CHP = 1 and CHP = 0 to the order of the
noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on the 80 mV range reduces the gain error to less than
100 ppm for the 80 mV and 40 mV ranges, to about 250 ppm for the 20 mV range and to about 500 ppm on the 10 mV range. System full-scale calibration reduces this to the order of
the noise. Positive and negative full-scale errors can be calculated from the offset and gain errors.
14
These numbers are generated during life testing of the part.
15
Positive Full-Scale Error includes Offset Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See Terminology.
16
Recalibration at any temperature will remove these errors.
17
Full-Scale Drift includes Offset Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
18
Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points used to calculate the gain
error are positive full scale and negative full scale. See Terminology.
19
Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed.
10
No Missing Codes performance with CHP = 0 and SKIP = 1 is reduced below 24 bits for SF words lower than 180 decimal.
11
The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs respectively.
12
The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.
13
The common-mode voltage range on the reference input pair (REF IN(+) and REF IN(–)) applies provided the absolute input voltage specification is obeyed.
14
These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.
15
V
DD
refers to DV
DD
for all logic outputs expect D0, D1, ACX and ACX where it refers to AV
DD
. In other words, the output logic high for these four outputs is determined by AV
DD
.
16
This number represents the total drift of the channel with a zero input and the DAC output near full scale.
17
After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, the device outputs all 0s.
18
These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the
bipolar zero point.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
to T
MAX
Parameter (B Version) Units Conditions/Comments
Master Clock Range 1 MHz min For Specified Performance
5 MHz max
t
1
50 ns min SYNC Pulsewidth
t
2
50 ns min RESET Pulsewidth
Read Operation
t
3
0 ns min RDY to CS Setup Time
t
4
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
3
t
5
4
0 ns min SCLK Active Edge to Data Valid Delay
3
60 ns max DV
DD
= +4.75 V to +5.25 V
80 ns max DV
DD
= +2.75 V to +3.3 V
t
5A
4, 5
0 ns min CS Falling Edge to Data Valid Delay
60 ns max DV
DD
= +4.75 V to +5.25 V
80 ns max DV
DD
= +2.7 V to +3.3 V
t
6
100 ns min SCLK High Pulsewidth
t
7
100 ns min SCLK Low Pulsewidth
t
8
0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time
3
t
9
6
10 ns min Bus Relinquish Time after SCLK Inactive Edge
3
80 ns max
t
10
100 ns max SCLK Active Edge to RDY High
3, 7
Write Operation
t
11
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
3
t
12
30 ns min Data Valid to SCLK Edge Setup Time
t
13
25 ns min Data Valid to SCLK Edge Hold Time
t
14
100 ns min SCLK High Pulsewidth
t
15
100 ns min SCLK Low Pulsewidth
t
16
0 ns min CS Rising Edge to SCLK Edge Hold Time
NOTES
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
2
See Figures 18 and 19.
3
SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.
4
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
5
This specification only comes into play if CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is primarily required for
interfacing to DSP machines.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
7
RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should
be taken that subsequent reads do not occur close to the next output update.
(AV
DD
= +4.75 V to +5.25 V; DV
DD
= +2.7 V to +5.25 V; AGND = DGND = 0 V; f
CLK IN
= 4.9152 MHz;
Input Logic 0 = 0 V, Logic 1 = DV
DD
unless otherwise noted).
REV. B
