AD7730/AD7730L
–49–
Table XXIII. Output Noise vs. Input Range and Update Rate (CHP = 0)
Typical Output RMS Noise in nV
Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range
Data Rate Frequency Word Normal Mode Fast Mode = 80 mV = 40 mV = 20 mV = 10 mV
75 Hz 2.9 Hz 2048 332 ms 53.2 ms 320 215 135 100
100 Hz 3.9 Hz 1536 250 ms 40 ms 325 245 160 110
150 Hz 5.85 Hz 1024 166 ms 26.6 ms 410 275 180 130
300 Hz 11.7 Hz 512 83 ms 13.3 ms 590 370 265 180
600 Hz 23.4 Hz 256 41.6 ms 6.6 ms 910 580 350 220
Table XXIV. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 0)
Peak-to-Peak Resolution in Counts (Bits)
Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range
Data Rate Frequency Word Normal Mode Fast Mode = 80 mV = 40 mV = 20 mV = 10 mV
75 Hz 2.9 Hz 2048 332 ms 53.2 ms 85k (16.5) 62k (16) 49k (15.5) 33k (15)
100 Hz 3.9 Hz 1536 250 ms 40 ms 82k (16.5) 55k (15.5) 42k (15.5) 30k (15)
150 Hz 5.85 Hz 1024 166 ms 26.6 ms 65k (16) 48k (15.5) 36k (15) 25k (14.5)
300 Hz 11.7 Hz 512 83 ms 13.3 ms 45k (15.5) 36k (15) 25k (14.5) 18k (14)
600 Hz 23.4 Hz 256 41.6 ms 6.63 ms 30k (15) 23k (14.5) 19k (14) 15k (14)
REV. B
AD7730/AD7730L
–50–
REV. A
PAGE INDEX
Topic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
AD7730 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . 2
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 4
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . . 6
SIGNAL PROCESSING CHAIN . . . . . . . . . . . . . . . . . . . . . 7
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . 7
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
OUTPUT NOISE AND RESOLUTION
SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Summary Of On-Chip Registers . . . . . . . . . . . . . . . . . . . . 12
Communications Register . . . . . . . . . . . . . . . . . . . . . . . . 13
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DAC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Offset Calibration Register . . . . . . . . . . . . . . . . . . . . . . . . 20
Gain Calibration Register . . . . . . . . . . . . . . . . . . . . . . . . . 20
Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
READING FROM AND WRITING TO THE
ON-CHIP REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . 21
CALIBRATION OPERATION SUMMARY . . . . . . . . . . . 22
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 23
ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REFERENCE INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SIGMA-DELTA MODULATOR . . . . . . . . . . . . . . . . . . . . 26
DIGITAL FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Filter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
First Stage Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Second Stage Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Internal Zero-Scale Calibration . . . . . . . . . . . . . . . . . . . . 30
Internal Full-Scale Calibration . . . . . . . . . . . . . . . . . . . . . 30
System Zero-Scale Calibration . . . . . . . . . . . . . . . . . . . . . 31
System Full-Scale Calibration . . . . . . . . . . . . . . . . . . . . . 31
Span and Offset Limits . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power-Up and Calibration . . . . . . . . . . . . . . . . . . . . . . . . 32
Drift Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
USING THE AD7730 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Clocking and Oscillator Circuit . . . . . . . . . . . . . . . . . . . . 32
System Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Single-Shot Conversions . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Evaluating the AD7730 Performance . . . . . . . . . . . . . . . . 34
SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CONFIGURING THE AD7730 . . . . . . . . . . . . . . . . . . . . . 37
MICROCOMPUTER/MICROPROCESSOR
INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AD7730 to 68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 38
AD7730 to 8051 Interface . . . . . . . . . . . . . . . . . . . . . . . . 38
AD7730 to ADSP-2105 Interface . . . . . . . . . . . . . . . . . . 39
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DC Excitation of Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC Excitation of Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Bipolar Excitation of Bridge . . . . . . . . . . . . . . . . . . . . . . . 42
APPENDIX A–AD7730L SPECIFICATIONS . . . . . . . . . . 43
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 51
TABLE INDEX
Table Title Page
Table I. Output Noise vs. Input Range and
Update Rate (CHP = 1) 10
Table II. Peak-to-Peak Resolution vs. Input Range
and Update Rate (CHP = 1) 10
Table III. Output Noise vs. Input Range and
Update Rate (CHP = 0) 11
Table IV. Peak-to-Peak Resolution vs. Input Range
and Update Rate (CHP = 0) 11
Table V. Summary of On-Chip Registers 12
Table VI. Communications Register 13
Table VII. Read/Write Mode 13
Table VIII. Register Selection 14
Table IX. Status Register 14
Table X. Mode Register 15
Table XI. Operating Modes 15
Table XII. Input Range Selection 17
Table XIII. Channel Selection 18
Table XIV. Filter Register 18
Table XV. SF Ranges 19
Table XVI. DAC Register 20
Table XVII. Calibration Operations 22
Table XVIII. Reset Events 23
Table XIX. Pseudo-Code for Initiating a
Self-Calibration after Power-On/Reset 37
Table XX. Pseudo-Code for Setting Up AD7730 for
Continuous Conversion and Continuous
Read Operation 37
Table XXI. Output Noise vs. Input Range and
Update Rate (CHP = 1) 48
Table XXII. Peak-to-Peak Resolution vs. Input Range
and Update Rate (CHP = 1) 48
Table XXIII. Output Noise vs. Input Range and
Update Rate (CHP = 0) 49
Table XXIV. Peak-to-Peak Resolution vs. Input Range
and Update Rate (CHP = 0) 49
52
AD7730/AD7730L
REV. B –51–
OUTLINE DIMENSIONS
24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001
071006-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
24
1
12
13
0.100 (2.54)
BSC
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
15.60 (0.6142)
15.20 (0.5984)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0
.
7
5
(
0
.
0
2
9
5
)
0
.
2
5
(
0
.
0
0
9
8
)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
24
13
12
1
1.27 (0.0500)
BSC
12-09-2010-A

AD7730BRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 24-Bit Bridge Transducer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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