AD7730LBRUZ-REEL7 Datasheet AD7730BRUZ, AD7730BNZ, AD7730BRZ | P19-P21

AD7730/AD7730L

–19–

Table XV. SF Ranges

CHOP SKIP SF Range Output Update Rate Range (Assuming 4.9152 MHz Clock)

0 0 2048 to 150 150 Hz to 2.048 kHz

1 0 2048 to 75 50 Hz to 1.365 kHz

0 1 2048 to 40 150 Hz to 7.6 kHz

1 1 2048 to 20 50 Hz to 5.12 kHz

Bit Bit

Location Mnemonic Description

FR11–FR10 ZERO A zero must be written to these bits to ensure correct operation of the AD7730.

FR9 SKIP FIR Filter Skip Bit. With a 0 in this bit, the AD7730 performs two stages of filtering before

shipping a result out of the filter. The first is a sinc

filter followed by a 22-tap FIR filter. With a

1 in this bit, the FIR filter on the part is bypassed and the output of the sinc

is fed directly

as the output result of the AD7730’s filter (see Filter Architecture for more details on the filter

implementation).

FR8 FAST FASTStep Mode Enable Bit. A 1 in this bit enables the FASTStep mode on the AD7730. In

this mode, if a step change on the input is detected, the FIR calculation portion of the filter is

suspended and replaced by a simple moving average on the output of the sinc

filter. Initially,

two outputs from the sinc

filter are used to calculate an AD7730 output. The number of sinc

outputs used to calculate the moving average output is increased (from 2 to 4 to 8 to 16) until

the STDY bit goes low. When the FIR filter has fully settled after a step, the STDY bit will

become active and the FIR filter is switched back into the processing loop (see Filter Architec-

ture section for more details on the FASTStep mode).

FR7–FR6 ZERO A zero must be written to these bits to ensure correct operation of the AD7730.

FR5 AC AC Excitation Bit. If the signal source to the AD7730 is ac-excited, a 1 must be placed in this

bit. For dc-excited inputs, this bit must be 0. The ac bit has no effect if CHP is 0. With the ac

bit at 1, the AD7730 assumes that the voltage at the AIN(+)/AIN(–) and REF IN(+)/REF IN(–)

input terminals are reversed on alternate input sampling cycles (i.e. chopped). Note that when

the AD7730 is performing internal zero-scale or full-scale calibrations, the ac bit is treated as a

0, i.e., the device performs these self-calibrations with dc excitation.

FR4 CHP Chop Enable Bit. This bit determines if the chopping mode on the part is enabled. A 1 in this

bit location enables chopping on the part. When the chop mode is enabled, the part is effectively

chopped at its input and output to remove all offset and offset drift errors on the part. If offset

performance with time and temperature are important parameters in the design, it is recom-

mended that the user enable chopping on the part. If the input signal is dc-excited, the user has

the option of operating the part in either chop or nonchop mode. If the input signal is ac-excited,

both the ac bit and the CHP bit must be set to 1. The chop rate on the ACX and ACX signals is

one half of the programmed output rate of the part and thus the chopping frequency varies with

the programmed output rate.

FR3–FR0 DL3–DL0 Delay Selection Bits. These four bits program the delay (in modulator cycles) to be inserted after

each chop edge when the CHP bit is 1. One modulator cycle is MCLK IN/16 and is 3.25 μs at

MCLK IN = 4.9152 MHz. A delay should only be required when in ac mode. Its purpose is to

cater for external delays between the switching signals (ACX and ACX) and when the analog

inputs are actually switched and settled. During the specified number of cycles (between 0 and

15), the modulator is held in reset and the filter does not accept any inputs. If CHP = 1, the

output rate is (MCLK IN/ 16 × (DL + 3 × SF) where DL is the value loaded to bits DL0–DL3.

The chop rate is always one half of the output rate. This chop period takes into account the

programmed delay and the fact that the sinc

filter must settle every chop cycle. With CHP = 0,

the output rate is 1/SF.

REV. B

AD7730/AD7730L

–20–

DAC Register (RS2–RS0 = 1, 0, 0); Power On/Reset Status: 20 Hex

The DAC Register is an 8-bit register from which data can either be read or to which data can be written. This register provides

the code for the offset-compensation DAC on the part. Table XVI outlines the bit designations for the DAC Register. DR0

through DR7 indicate the bit location, DR denoting the bits are in the DAC Register. DR7 denotes the first bit of the data

stream. The number in brackets indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading

from the registers on the AD7730 and Figure 6 shows a flowchart for writing to the registers on the part.

Table XVI. DAC Register

DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0

ZERO (0) ZERO (0) DAC5 (1) DAC4 (0) DAC3 (0) DAC2 (0) DAC1 (0) DAC0 (0)

Bit Bit

Location Mnemonic Description

DR7–DR6 ZERO A zero must be written to these bits to ensure correct operation of the AD7730.

DR5–DR0 DAC5–DAC0 DAC Selection Bits. These bits program the output of the offset DAC. The DAC is effectively

6 bits with one sign bit (DAC5) and five magnitude bits. With DAC5 at 1, the DAC output

subtracts from the analog input before it is applied to the PGA. With DAC5 at 0, the DAC

output adds to the analog input before it is applied to the PGA. The DAC output is given by

REF

/62.5) × (D/32) = (V

REF

/2000) × D where D is the decimal equivalent of bits DAC4 to

DAC0. Thus, for a 5 V reference applied across the REF IN pins, the DAC resolution is 2.5 mV

and offsets in the range –77.5 mV to +77.5 mV can be removed from the analog input signal

before it is applied to the PGA. Note, that the HIREF bit has no effect on the DAC range or

resolution, it controls the ADC range only.

Offset Calibration Register (RS2–RS0 = 1, 0, 1); Power-On/Reset Status: 800000 Hex

The AD7730 contains three 24-bit Offset Calibration Registers, labelled Offset Calibration Register 0 to Offset Calibration Reg-

ister 2, to which data can be written and from which data can be read. The three registers are totally independent of each other.

The Offset Calibration Register is used in conjunction with the associated Gain Calibration Register to form a register pair. The

calibration register pair used to scale the output is as outlined in Table XIII. The Offset Calibration Register is updated after an

offset calibration routine (1, 0, 0 or 1, 1, 0 loaded to the MD2, MD1, MD0 bits of the Mode Register). During subsequent

conversions, the contents of this register are subtracted from the filter output prior to gain scaling being performed on the word.

Figure 5 shows a flowchart for reading from the registers on the AD7730 and Figure 6 shows a flowchart for writing to the regis-

ters on the part.

Gain Calibration Register (RS2–RS0 = 1, 1, 0); Power-On/Reset Status: 593CEA

The AD7730 contains three 24-bit Gain Calibration Registers, labelled Gain Calibration Register 0 to Gain Calibration Register

2, to which data can be written and from which data can be read. The three registers are totally independent of each other. The

Gain Calibration Register is used in conjunction with the associated Offset Calibration Register to form a register pair. The

calibration register pair used to scale the output is as outlined in Table XIII. The Gain Calibration Register is updated after a

gain calibration routine (1, 0, 1 or 1, 1, 1 loaded to the MD2, MD1, MD0 bits of the Mode Register). During subsequent con-

versions, the contents of this register are used to scale the number which has already been offset corrected with the Offset Cali-

bration Register contents. Figure 5 shows a flowchart for reading from the registers on the AD7730 and Figure 6 shows a

flowchart for writing to the registers on the part.

Test Register (RS2–RS0 = 1, 1, 1); Power-On/Reset Status: 000000Hex

The AD7730 contains a 24-bit Test Register to which data can be written and from which data can be read. The contents of this

Test Register are used in testing the device. The user is advised not to change the status of any of the bits in this register from the

default (Power-On or RESET) status of all 0s as the part will be placed in one of its test modes and will not operate correctly. If the

part enters one of its test modes, exercising RESET or writing 32 successive 1s to the part will exit the AD7730 from the mode and

return all register contents to their power-on/reset status. Note, if the part is placed in one of its test modes, it may not be possible to

read back the contents of the Test Register depending on the test mode in which the part has been placed.

REV. B

AD7730/AD7730L

–21–

READING FROM AND WRITING TO THE ON-CHIP REGISTERS

The AD7730 contains a total of thirteen on-chip registers. These registers are all accessed over a three-wire interface. As a result,

addressing of registers is via a write operation to the topmost register on the part, the Communications Register. Figure 5 shows a

flowchart for reading from the different registers on the part summarizing the sequence and the words to be written to access each of

the registers. Figure 6 gives a flowchart for writing to the different registers on the part, again summarizing the sequence and words

to be written to the AD7730.

Figure 5. Flowchart for Reading from the AD7730 Registers

Figure 6. Flowchart for Writing to the AD7730 Registers

Communications Register 00

Data Register Read Only Register

Mode Register 02

Filter Register 03

DAC Register 04

Offset Register 05

Gain Register 06

Test Register User is advised not to change

contents of Test Register.

Byte W Byte Y Byte Z

Status Register 10 20 30

Data Register 11 21 30

Mode Register 12 22 30

Filter Register 13 N/A* N/A*

DAC Register 14 N/A* N/A*

Offset Register 15 N/A* N/A*

Gain Register 16 N/A* N/A*

Test Register 17 N/A* N/A*

*N/A= Not Applicable. Continuous reads of these registers does not make sense

as the register contents would remain the same since they are only changed by a

write operation.

START

WRITE

BYTE W

COMMUNICATIONS REGISTER

(SEE ACCOMPANYING TABLE)

YES

READ REGISTER

WRITE

BYTE Y

COMMUNICATIONS REGISTER

(SEE ACCOMPANYING TABLE)

READ REGISTER

YES

WRITE

BYTE Z

COMMUNICATIONS REGISTER

(SEE ACCOMPANYING TABLE)

STOP

CONTINUOUS

READ

OPERATION?

CONTINUOUS

READS OF

REQUIRED?

START

WRITE

BYTE Y

COMMUNICATIONS REGISTER

(SEE ACCOMPANYING TABLE)

WRITE TO REGISTER

END

REV. B

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P53

AD7730LBRUZ-REEL7

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC CMOS 24-Bit Low Pwr

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AD7730LBRUZ-REEL7

AD7730LBRUZ-REEL7

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