AD7730LBRUZ-REEL7 Datasheet AD7730BRUZ, AD7730BNZ, AD7730BRZ | P7-P9

AD7730/AD7730L

–7–

Figure 3. Signal Processing Chain

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

No. Mnemonic Function

1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer serial

data to or from the AD7730. This serial clock can be a continuous clock with all data transmitted in a con-

tinuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted

to or from the AD7730 in smaller batches of data.

2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A

crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin

can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The AD7730 is specified

with a clock input frequency of 4.9152 MHz while the AD7730L is specified with a clock input frequency of

2.4576 MHz.

SCLK

MCLK IN

DGND

SYNC

BIAS

RDY

MCLK OUT

POL

DIN

DOUT

AGND

ACX

AIN1(+)

STANDBY

TOP VIEW

(Not to Scale)

12 13

AD7730

RESET

REF IN(–)

REF IN(+)

AIN1(–)

AIN2(+)/D1

AIN2(–)/D0

ACX

PGA +

SIGMA-DELTA

MODULATOR

SINC

FILTER

CHOP

22-TAP

FIR FILTER

FASTSTEP

FILTER

CHOP

INPUT CHOPPING

THE ANALOG INPUT TO THE PART CAN BE

CHOPPED. IN CHOPPING MODE, WITH

AC EXCITATION DISABLED, THE INPUT

CHOPPING IS INTERNALTO THE DEVICE. IN

CHOPPING MODE, WITH AC EXCITATION

ENABLED, THE CHOPPING IS ASSUMED

TO BE PERFORMED EXTERNAL TO THE PART

AND NO INTERNAL INPUT CHOPPING IS

PERFORMED. THE INPUT CHOPPING CAN

BE DISABLED, IF DESIRED.

SEE PAGE 26

ANALOG

INPUT

DIGITAL

OUTPUT

SINC

FILTER

THE FIRST STAGE OF THE DIGITAL FILTERING

ON THE PART IS THE SINC

FILTER. THE

OUTPUT UPDATE RATE AND BANDWIDTH

OF THIS FILTER CAN BE PROGRAMMED. IN

SKIP MODE, THE SINC

FILTER IS THE

ONLY FILTERING PERFORMED ON THE PART.

SEE PAGE 26

BUFFER

SKIP MODE

IN SKIP MODE, THERE IS NO SECOND

STAGE OF FILTERING ON THE PART. THE

SINC

FILTER IS THE ONLY FILTERING

PERFORMED ON THE PART.

SEE PAGE 29

SKIP

OUTPUT

SCALING

22-TAP FIR FILTER

IN NORMAL OPERATING MODE, THE

SECOND STAGE OF THE DIGITAL FILTERING

ON THE PART IS A FIXED 22-TAP FIR

FILTER. IN SKIP MODE, THIS FIR FILTER IS

BYPASSED. WHEN FASTSTEP™

MODE IS

ENABLED AND A STEP INPUT IS

DETECTED, THE SECOND STAGE FILTERING

IS PERFORMED BY THE FILTER

UNTIL THE OUTPUT OF THIS FILTER

HAS FULLY SETTLED.

SEE PAGE 27

OUTPUT SCALING

THE OUTPUT WORD FROM THE DIGITAL

FILTER IS SCALED BY THE CALIBRATION

COEFFICIENTS BEFORE BEING PROVIDED

AS THE CONVERSION RESULT.

SEE PAGE 29

FASTSTEP FILTER

WHEN FASTSTEP MODE IS ENABLED

AND A STEP CHANGE ON THE INPUT

HAS BEEN DETECTED, THE SECOND

STAGE FILTERING IS PERFORMED BY THE

FASTSTEP FILTER UNTIL THE FIR

FILTER HAS FULLY SETTLED.

SEE PAGE 29

OUTPUT CHOPPING

THE OUTPUT OF THE FIRST STAGE

OF FILTERING ON THE PART CAN

BE CHOPPED. IN CHOPPING MODE,

REGARDLESS OF WHETHER AC

EXCITATION IS ENABLED OR DISABLED,

THE OUTPUT CHOPPING IS

PERFORMED. THE CHOPPING CAN

BE DISABLED, IF DESIRED.

SEE PAGE 26

PGA + SIGMA-DELTA MODULATOR

THE PROGRAMMABLE GAIN CAPABILITY

OF THE PART IS INCORPORATED

AROUND THE SIGMA-DELTA MODULATOR.

THE MODULATOR PROVIDES A HIGH-

FREQUENCY 1-BIT DATA STREAM

TO THE DIGITAL FILTER.

SEE PAGE 26

BUFFER

THE INPUT SIGNAL IS BUFFERED

ON-CHIP BEFORE BEING APPLIED TO

THE SAMPLING CAPACITOR OF THE

SIGMA-DELTA MODULATOR. THIS

ISOLATES THE SAMPLING CAPACITOR

CHARGING CURRENTS FROM THE

ANALOG INPUT PINS.

SEE PAGE 24

REV. B

AD7730/AD7730L

–8–

No. Mnemonic Function

3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN

and MCLK OUT. If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock sig-

nal. This clock can be used to provide a clock source for external circuits and MCLK OUT is capable of driving

one CMOS load. If the user does not require it, MCLK OUT can be turned off with the CLKDIS bit of the Mode

4 POL Clock Polarity. Logic Input. This determines the polarity of the serial clock. If the active edge for the proces-

sor is a high-to-low SCLK transition, this input should be low. In this mode, the AD7730 puts out data on the

DATA OUT line in a read operation on a low-to-high transition of SCLK and clocks in data from the DATA

IN line in a write operation on a high-to-low transition of SCLK. In applications with a noncontinuous serial

clock (such as most microcontroller applications), this means that the serial clock should idle low between

data transfers. If the active edge for the processor is a low-to-high SCLK transition, this input should be high.

In this mode, the AD7730 puts out data on the DATA OUT line in a read operation on a high-to-low transi-

tion of SCLK and clocks in data from the DATA IN line in a write operation on a low-to-high transition of

SCLK. In applications with a noncontinuous serial clock (such as most microcontroller applications), this

means that the serial clock should idle high between data transfers.

5 SYNC Logic Input that allows for synchronization of the digital filters and analog modulators when using a number

of AD7730s. While SYNC is low, the nodes of the digital filter, the filter control logic and the calibration

control logic are reset and the analog modulator is also held in its reset state. SYNC does not affect the digital

interface but does reset RDY to a high state if it is low. While SYNC is asserted, the Mode Bits may be set up

for a subsequent operation which will commence when the SYNC pin is deasserted.

6 RESET Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator and

all on-chip registers of the part to power-on status. Effectively, everything on the part except for the clock

oscillator is reset when the RESET pin is exercised.

BIAS

Analog Output. This analog output is an internally-generated voltage used as an internal operating bias point.

This output is not for use external to the AD7730 and it is recommended that the user does not connect any-

thing to this pin.

8 AGND Ground reference point for analog circuitry.

9AV

Analog Positive Supply Voltage. The AV

to AGND differential is 5 V nominal.

10 AIN1(+) Analog Input Channel 1. Positive input of the differential, programmable-gain primary analog input pair. The

differential analog input ranges are 0 mV to +10 mV, 0 mV to +20 mV, 0 mV to +40 mV and 0 mV to +80 mV

in unipolar mode, and ±10 mV, ± 20 mV, ± 40 mV and ± 80 mV in bipolar mode.

11 AIN1(–) Analog Input Channel 1. Negative input of the differential, programmable gain primary analog input pair.

12 AIN2(+)/D1 Analog Input Channel 2 or Digital Output 1. This pin can be used either as part of a second analog input

channel or as a digital output bit as determined by the DEN bit of the Mode Register. When selected as an

analog input, it is the positive input of the differential, programmable-gain secondary analog input pair. The

analog input ranges are 0 mV to +10 mV, 0 mV to +20 mV, 0 mV to +40 mV and 0 mV to +80 mV in unipo-

lar mode and ±10 mV, ± 20 mV, ±40 mV and ± 80 mV in bipolar mode. When selected as a digital output,

this output can programmed over the serial interface using bit D1 of the Mode Register.

13 AIN2(–)/D0 Analog Input Channel 2 or Digital Output 0. This pin can be used either as part of a second analog input channel

or as a digital output bit as determined by the DEN bit of the Mode Register. When selected as an analog input, it

is the negative input of the differential, programmable-gain secondary analog input pair. When selected as a digital

output, this output can programmed over the serial interface using bit D0 of the Mode Register.

14 REF IN(+) Reference Input. Positive terminal of the differential reference input to the AD7730. REF IN(+) can lie

anywhere between AV

and AGND. The nominal reference voltage (the differential voltage between REF

IN(+) and REF IN(–)) should be +5 V when the HIREF bit of the Mode Register is 1 and +2.5 V when the

HIREF bit of the Mode Register is 0.

15 REF IN(–) Reference Input. Negative terminal of the differential reference input to the AD7730. The REF IN(–) poten-

tial can lie anywhere between AV

and AGND.

16 ACX Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac-

excited bridge applications. When ACX is high, the bridge excitation is taken as normal and when ACX is

low, the bridge excitation is reversed (chopped). If AC = 0 (ac mode turned off) or CHP = 0 (chop mode

turned off), the ACX output remains high.

17 ACX Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac-

excited bridge applications. This output is the complement of ACX. In ac mode, this means that it toggles in

anti-phase with ACX . If AC = 0 (ac mode turned off) or CHP = 0 (chop mode turned off), the ACX output

remains low. When toggling, it is guaranteed to be nonoverlapping with ACX. The non-overlap interval, when

both ACX and ACX are low, is one master clock cycle.

REV. B

AD7730/AD7730L

–9–

No. Mnemonic Function

18 STANDBY Logic Input. Taking this pin low shuts down the analog and digital circuitry, reducing current consumption to

the 5 μA range. The on-chip registers retain all their values when the part is in standby mode.

19 CS Chip Select. Active low Logic Input used to select the AD7730. With this input hardwired low, the AD7730

can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the device. CS

can be used to select the device in systems with more than one device on the serial bus or as a frame synchro-

nization signal in communicating with the AD7730.

20 RDY Logic Output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a

logic low on this output indicates that a new output word is available from the AD7730 data register. The

RDY pin will return high upon completion of a read operation of a full output word. If no data read has taken

place after an output update, the RDY line will return high prior to the next output update, remain high while

the update is taking place and return low again. This gives an indication of when a read operation should not

be initiated to avoid initiating a read from the data register as it is being updated. In calibration mode, RDY

goes high when calibration is initiated and it returns low to indicate that calibration is complete. A number of

different events on the AD7730 set the RDY high and these are outlined in Table XVIII.

21 DOUT Serial Data Output with serial data being read from the output shift register on the part. This output shift

DAC register or data register, depending on the register selection bits of the Communications Register.

22 DIN Serial Data Input with serial data being written to the input shift register on the part. Data from this input

shift register is transferred to the calibration registers, mode register, communications register, DAC register

or filter registers depending on the register selection bits of the Communications Register.

23 DV

Digital Supply Voltage, +3 V or +5 V nominal.

24 DGND Ground reference point for digital circuitry.

TERMINOLOGY

INTEGRAL NONLINEARITY

This is the maximum deviation of any code from a straight line

passing through the endpoints of the transfer function. The end-

points of the transfer function are zero scale (not to be confused

with bipolar zero), a point 0.5 LSB below the first code transi-

tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB

above the last code transition (111 . . . 110 to 111 . . . 111). The

error is expressed as a percentage of full scale.

POSITIVE FULL-SCALE ERROR

Positive Full-Scale Error is the deviation of the last code transition

(111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage

(AIN(–) + V

REF

/GAIN – 3/2 LSBs). It applies to both unipolar

and bipolar analog input ranges. Positive full-scale error is a

summation of offset error and gain error.

UNIPOLAR OFFSET ERROR

Unipolar Offset Error is the deviation of the first code transition

from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-

ating in the unipolar mode.

BIPOLAR ZERO ERROR

This is the deviation of the midscale transition (0111 . . . 111 to

1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) – 0.5 LSB)

when operating in the bipolar mode.

GAIN ERROR

This is a measure of the span error of the ADC. It is a measure

of the difference between the measured and the ideal span be-

tween any two points in the transfer function. The two points

used to calculate the gain error are full scale and zero scale.

BIPOLAR NEGATIVE FULL-SCALE ERROR

This is the deviation of the first code transition from the ideal

AIN(+) voltage (AIN(–) – V

REF

/GAIN + 0.5 LSB) when operat-

ing in the bipolar mode. Negative full-scale error is a summation

of zero error and gain error.

POSITIVE FULL-SCALE OVERRANGE

Positive Full-Scale Overrange is the amount of overhead avail-

able to handle input voltages on AIN(+) input greater than

AIN(–) + V

REF

/GAIN (for example, noise peaks or excess volt-

ages due to system gain errors in system calibration routines) with-

out introducing errors due to overloading the analog modulator

or overflowing the digital filter.

NEGATIVE FULL-SCALE OVERRANGE

This is the amount of overhead available to handle voltages on

AIN(+) below AIN(–) – V

REF

/GAIN without overloading the

analog modulator or overflowing the digital filter.

OFFSET CALIBRATION RANGE

In the system calibration modes, the AD7730 calibrates its

offset with respect to the analog input. The Offset Calibration

Range specification defines the range of voltages the AD7730

can accept and still accurately calibrate offset.

FULL-SCALE CALIBRATION RANGE

This is the range of voltages that the AD7730 can accept in the

system calibration mode and still calibrate full scale correctly.

INPUT SPAN

In system calibration schemes, two voltages applied in sequence

to the AD7730’s analog input define the analog input range.

The input span specification defines the minimum and maxi-

mum input voltages, from zero to full scale, the AD7730 can

accept and still accurately calibrate gain.

REV. B

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P53

AD7730LBRUZ-REEL7

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC CMOS 24-Bit Low Pwr

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AD7730LBRUZ-REEL7

AD7730LBRUZ-REEL7

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