NCP13992
www.onsemi.com
13
Figure 8. Internal Connection of the NCP13992 Current Mode Control Scheme
The basic principle of current mode control scheme
implementation lies in the use of an ON−time comparator
that defines upper switch on−time by comparing voltage
ramp, derived from the current sense input voltage, to the
divided feedback pin voltage. The upper switch on−time is
then re−used for low side switch conduction period. The
switching frequency is thus defined by the actual primary
current and output load conditions. Digital processing with
10 ns minimum on−time resolution is implemented to
ensure high noise immunity. The ON−time comparator
output is blanked by the leading edge blanking (t
LEB
) after
the Mupper switch is turned−on. The ON−time comparator
LEB period helps to avoid false triggering of the on−time
modulation due to noise generated by the HB pin voltage
transition.
The voltage signal for current sense input is prepared
externally via natural primary current integration by the
resonant tank capacitor Cs. The resonant capacitor voltage
is divided down by capacitive divider (Ccs1, Ccs2, Rcs1,
Rcs2) before it is provided to the CS input. The capacitive
divider division ratio, which is fully externally adjustable,
defines the maximum primary current level that is reached
in case of maximum feedback voltage – i.e. the capacitive
divider division ration defines the maximum output power
of the converter for given bulk voltage. The CS is a bipolar
input pin which an input voltage swing is restricted to ±5V.
A fixed voltage offset is internally added to the CS pin signal
in order to assure enough voltage margin for operation the
feedback optocoupler − the FB optocoupler saturation
voltage is ~ 0.15 V (depending on type). However, the CS
pin useful signal for frequency modulation swings from 0 V,
so current mode regulation would not work under light load
conditions if no offset would be added to the CS pin before
it is stabilized to the level of the on−time comparator input.
The CS pin signal is also used for secondary side short circuit
detection – please refer to chapter dedicated to short circuit
protection.
The second input signal for the on−time comparator is
derived from the FB pin voltage. This internal FB pin signal
is also used for the following purposes: skip mode operation
detection, PFC MODE control and overload / open FB pin
fault detection. The detailed description of these functions
can be found in each dedicated chapters. The internal
pull−up resistor assures that the FB pin voltage increases
when the optocoupler LED becomes less biased – i.e. when
output load is increased. The higher FB pin voltage implies
a higher reference level for on−time comparator i.e. longer
Mupper switch on−time and thus also higher output power.
The FB pin features a precise voltage clamp which limits the
internal FB signal during overload and startup. The FB pin
signal passes through the FB processing block before it is
brought to the ON−time comparator input. The FB
processing block scales the FB signal down by a K
FB
ratio
in order to limit the CS input dynamic voltage range. The
scaled FB signal is then further processed by subtraction of
a ramp compensation generator signal in order to ensure
stability of the current mode control scheme. The divided
internal FB signal is overridden by a Soft−start generator
output voltage during device starts−up.
The actual operating frequency of the converter is defined
based on the CS pin and FB pin input signals. The maximum
output power of the converter, under given input voltage, is
limited by maximum internal FB voltage clamp that is
reached when optocoupler provides no current. The
maximum output power limit is bulk voltage dependent due
to changing ratio between magnetizing and load primary
current components. Line Feed Forward (LFF) system is
implemented in the controller to compensate for maximum
output power clamp variation. The I
LFF
current that flows
out from the Cs pin is BO/PFC FB pin voltage proportional
