3
IDT72V70800 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
SYMBOL NAME I/O DESCRIPTION
GND Ground. Ground Rail.
Vcc Vcc +3.3 Volt Power Supply.
TX0-3 TX Output 0 to 3 O Serial data output stream. These streams have a data rate of 8.192 Mb/s.
(Three-state Outputs)
RX0-3 RX Input 0 to 3 I Serial data input stream. These streams have a data rate of 8.192 Mb/s.
F0i Frame Pulse I When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals formatted
according to ST-BUS
®
and GCI specifications. When the WFPS pin is HIGH, this pin accepts a negative frame
pulse which conforms to WFPS formats.
FE/HCLK Frame Evaluation/ I When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK
HCLK Clock (4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode.
CLK Clock I Serial clock for shifting data in/out on the serial streams (RX/TX 0-3). This input accepts a 16.384 MHz clock.
RESET Device Reset I This input (active LOW) puts the IDT72V70800 in its reset state that clears the device internal counters, registers
(Schmitt Trigger Input) and brings TX0-3 and microport data outputs to a high-impedance state. The time constant for a power
up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the
RESET pin must be held LOW for a minimum of 100ns to reset the device.
WFPS Wide Frame I When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in
Pulse Select ST-BUS
®
/GCI mode.
A0-7 Address 0-7 I When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.
DS/RD Data Strobe/Read I For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with CS
to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This
active LOW input works in conjunction with CS to enable the read and write operations. For Intel multiplexed bus
operation, this input is RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.
R/W / WR Read/Write / Write I In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls
the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus
operation, this input is WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs.
CS Chip Select I Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70800.
AS/ALE Address Strobe or I This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed
Latch Enable bus operation, connect this pin to ground.
IM CPU Interface Mode I When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor
port is in non-multiplexed mode.
AD0-7 Address/Data Bus 0 to 7 I/O These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins
are also the input address bits of the microprocessor port.
D8-15 Data Bus 8-15 I/O These pins are the eight most significant data bits of the microprocessor port.
DTA Data Transfer O This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
Acknowledgment drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
ODE Output Drive Enable I This is the output enable control for the TX0 to TX3 serial outputs. When ODE input is LOW and the OSB
bit of the IMS register is LOW, TX0-3 are in a high-impedance state. If this input is HIGH, the TX0-3
output drivers are enabled. However, each channel may still be put into a high-impedance state by using
the per channel control bit in the connection memory.
