14
COMMERCIAL TEMPERATURE RANGE
IDT72V70800 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 512
AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLK
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
.
Symbol Characteristics Min. Typ. Max. Units
t
FPW Frame Pulse Width (ST-BUS
®
, GCI) ⎯ Bit rate = 8.192 Mb/s 26 ⎯ 80 ns
t
FPS Frame Pulse Setup time before CLK falling (ST-BUS
®
or GCI) 5 ⎯⎯ns
t
FPH Frame Pulse Hold Time from CLK falling (ST-BUS
®
or GCI) 10 ⎯⎯ns
t
CP CLK Period ⎯ Bit rate = 8.192 Mb/s 55 ⎯ 70 ns
t
CH CLK Pulse Width HIGH ⎯ Bit rate = 8.192 Mb/s 20 40 ns
t
CL CLK Pulse Width LOW ⎯ Bit rate = 8.192 Mb/s 20 ⎯ 40 ns
t
r, tf Clock Rise/Fall Time ⎯⎯ 10 ns
t
HFPW Wide Frame Pulse Width ⎯ Bit rate = 8.192 Mb/s 195 ⎯ 295 ns
t
HFPS Frame Pulse Setup Time before HCLK falling 5 ⎯ 150 ns
t
HFPH Frame Pulse Hold Time from HCLK falling 10 ⎯ 150 ns
t
HCP HCLK (4.096 MHz) Period ⎯ Bit rate = 8.192 Mb/s 190 ⎯ 300 ns
t
HCH HCLK (4.096 MHz) Pulse Width HIGH ⎯ Bit rate = 8.192 Mb/s 85 ⎯ 150 ns
t
HCL HCLK (4.096 MHz) Pulse Width LOW ⎯ Bit rate = 8.192 Mb/s 85 ⎯ 150 ns
t
Hr, tHf HCLK Rise/Fall Time ⎯⎯ 10 ns
t
DIF Delay between falling edge of HCLK and falling edge of CLK -10 ⎯ 10 ns
Symbol Characteristics Min. Typ. Max. Unit Test Conditions
t
SIS RX Setup Time 0 ⎯⎯ ns
t
SIH RX Hold Time 10 ⎯⎯ ns
t
SOD TX Delay – Active to Active
⎯⎯ 30 ns C
L
= 30pF
⎯⎯40 ns C
L
= 200pF
t
DZ TX Delay – Active to High-Z ⎯⎯32 ns R
L
= 1KΩ, C
L
= 200pF
t
ZD TX Delay – High-Z to Active ⎯⎯32 ns R
L
= 1KΩ, C
L
= 200pF
t
ODE Output Driver Enable (ODE) Delay ⎯⎯32 ns R
L
= 1KΩ, C
L
= 200pF
AC ELECTRICAL CHARACTERISTICS - SERIAL STREAMS
(1)
