72V70800TFG Datasheet 72V70800PFG, 72V70800PFG8, 72V70800TFG | P4-P6

COMMERCIAL TEMPERATURE RANGE

IDT72V70800 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 512 x 512

FUNCTIONAL DESCRIPTION

The IDT72V70800 is capable of switching up to 512 x 512, 64 Kbit/s PCM

or N x 64 Kbit/s channel data. The device maintains frame integrity in data

applications and minimum throughput delay for voice applications on a per

channel basis.

The serial input streams of the IDT72V70800 have a bit rate of 8.192 Mb/s

and are arranged in 125ms wide frames, which contain 128 channels. The data

rates on input and output streams are identical.

In Processor Mode, the microprocessor can access input and output time-

slots on a per channel basis allowing for transfer of control and status information.

The IDT72V70800 automatically identifies the polarity of the frame synchroni-

zation input signal and configures the serial streams to either ST-BUS

or GCI

formats.

With the variety of different microprocessor interfaces, IDT72V70800 has

provided an Input Mode pin (IM) to help integrate the device into different

microprocessor based environments: Non-multiplexed or Multiplexed. These

interfaces provide compatibility with multiplexed and Motorola non-multiplexed

buses. The device can also resolve different control signals eliminating the use

of glue logic necessary to convert the signals (R/W/WR, DS/RD, AS/ALE).

The frame offset calibration function allows users to measure the frame offset

delay using a frame evaluation pin (FE). The input offset delay can be

programmed for individual streams using internal frame input offset registers, see

Table 8.

The internal loopback allows the TX output data to be looped around to the

RX inputs for diagnostic purposes.

A functional Block Diagram of the IDT72V70800 is shown in Figure 1.

DATA AND CONNECTION MEMORY

The received serial data is converted to parallel format by internal serial-

to-parallel converters and stored sequentially in the data memory. The 8 KHz

input frame pulse (F0i) is used to generate channel and frame boundaries of

the input serial data. Depending on the interface mode select (IMS) register,

the usable data memory may be as large as 512 bytes.

Data to be output on the serial streams (TX0-3) may come from either the

data memory or connection memory. For data output from data memory

(connection mode), addresses in the connection memory are used. For data

to be output from connection memory, the connection memory control bits must

set the particular TX output in Processor Mode. One time-slot before the data

is to be output, data from either connection memory or data memory is read

internally. This allows enough time for memory access and parallel-to-serial

conversion.

CONNECTION AND PROCESSOR MODES

In the Connection Mode, the addresses of the input source data for all output

channels are stored in the connection memory. The connection memory is

mapped in such a way that each location corresponds to an output channel on

the output streams. For details on the use of the source address data (CAB and

SAB bits), see Table 10. Once the source address bits are programmed by the

microprocessor, the contents of the data memory at the selected address are

transferred to the parallel-to-serial converters and then onto a TX output stream.

By having the each location in the connection memory specify an input

channel, multiple outputs can specify the same input address. This can be a

powerful tool used for broadcasting data.

In Processor Mode, the microprocessor writes data to the connection

memory. Each location in the connection memory corresponds to a particular

output stream and channel number and is transferred directly to the parallel-to-

serial converter one time-slot before it is to be output. This data will be output

on the TX streams in every frame until the data is changed by the microprocessor.

As the IDT72V70800 can be used in a wide variety of applications, the device

also has memory locations to control the outputs based on operating mode.

Specifically, the IDT72V70800 provides five per-channel control bits for the

following functions: processor or connection mode, constant or variable delay,

enables/three-state the TX output drivers and enables/disable the loopback

function. In addition, one of these bits allows the user to control the CCO output.

If an output channel is set to a high-impedance state through the connection

memory, the TX output will be in a high-impedance state for the duration of that

channel. In addition to the per-channel control, all channels on the ST-BUS

outputs can be placed in a high impedance state by either pulling the ODE input

pin low or programming the Output Stand-By (OSB) bit in the interface mode

selection register. This action overrides the per-channel programming in the

connection memory bits.

The connection memory data can be accessed via the microprocessor

interface. The addressing of the devices internal registers, data and connection

memories is performed through the address input pins and the Memory Select

(MS) bit of the control register. For details on device addressing, see Software

Control and Control Register bits description (Table 3 and 5).

SERIAL DATA INTERFACE TIMING

The master clock frequency must always be twice the data rate. For serial

data rates of 8.192 Mb/s, the master clock (CLK) must be 16.384 MHz. The input

and output stream data rates will always be identical.

The IDT72V70800 provides two different interface timing modes ST-BUS

GCI and WFP (wide frame pulse). If the WFPS pin is high, the IDT72V70800

is in the wide frame pulse (WFP) frame alignment mode.

In ST-BUS

/GCI mode, the input 8 KHz frame pulse can be in either

ST-BUS

or GCI format. The IDT72V70800 automatically detects the presence

of an input frame pulse and identifies it as either ST-BUS

or GCI. In ST-BUS

format, every second falling edge of the master clock marks a bit boundary and

the data is clocked in on the rising edge of CLK, three quarters of the way into

the bit cell, see Figure 7. In GCI format, every second rising edge of the master

clock marks the bit boundary and data is clocked in on the falling edge of CLK

at three quarters of the way into the bit cell, see Figure 8.

WIDE FRAME PULSE (WFP) FRAME ALIGNMENT TIMING

When the device is in WFP frame alignment mode, the CLK input must be

at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 KHz frame pulse

is in ST-BUS

format. The timing relationship between CLK, HCLK and the frame

pulse is shown in Figure 9.

When WFPS pin is high, the frame alignment evaluation feature is disabled.

However, the frame input offset registers may still be programmed to compensate

for the varying frame delays on the serial input streams.

INPUT FRAME OFFSET SELECTION

Input frame offset selection allows the channel alignment of individual input

streams to be offset with respect to the output stream channel alignment (i.e. F0i).

Although all input data comes in at the same speed, delays can be caused by

variable path serial backplanes and variable path lengths which may be

implemented in large centralized and distributed switching systems. Because

data is often delayed, this feature is useful in compensating for the skew between

clocks.

Each input stream can have its own delay offset value by programming the

frame input offset registers (FOR). The maximum allowable skew is +4.5 master

IDT72V70800 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 512 x 512

COMMERCIAL TEMPERATURE RANGE

clock (CLK) periods forward with resolution of ½ clock period. The output frame

offset cannot be offset or adjusted. See Figure 5, Table 8 and 9 for delay offset

programming.

SERIAL INPUT FRAME ALIGNMENT EVALUATION

The IDT72V70800 provides the frame evaluation (FE) input to determine

different data input delays with respect to the frame pulse F0i.

A measurement cycle is started by setting the start frame evaluation (SFE)

bit low for at least one frame. When the SFE bit in the IMS register is changed

from low to high, the evaluation starts. Two frames later, the complete frame

evaluation (CFE) bit of the frame alignment register (FAR) changes from low

to high to signal that a valid offset measurement is ready to be read from bits 0

to 11 of the FAR register. The SFE bit must be set to zero before a new

measurement cycle started.

In ST-BUS

mode, the falling edge of the frame measurement signal (FE)

is evaluated against the falling edge of the ST-BUS

frame pulse. In GCI mode,

the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.

See Table 7 & Figure 4 for the description of the frame alignment register.

This feature is not available when the WFP Frame Alignment mode is

enabled (i.e., when the WFPS pin is connected to VCC).

MEMORY BLOCK PROGRAMMING

The IDT72V70800 provides users with the capability of initializing the entire

connection memory block in two frames. To set bits 11 to 15 of every connection

memory location, first program the desired pattern in bits 5 to 9 of the IMS register.

The block programming mode is enabled by setting the memory block

program (MBP) bit of the control register high. When the block programming

enable (BPE) bit of the IMS register is set to high, the block programming data

will be loaded into the bits 11 to 15 of every connection memory location. The

other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the

memory block programming is complete, the device resets the BPE bit to zero.

LOOPBACK CONTROL

The loopback control (LPBK) bit of each connection memory location allows

the TX output data to be looped backed internally to the RX input for diagnostic

purposes.

If the LPBK bit is high, the associated TX output channel data is internally

looped back to the RX input channel (i.e., data from TX n channel m routes to

the RX n channel m internally); if the LPBK bit is low, the loopback feature is

disabled. For proper per-channel loopback operation, the contents of frame

delay offset registers must be set to zero.

DELAY THROUGH THE IDT72V70800

The switching of information from the input serial streams to the output serial

streams results in a throughput delay. The device can be programmed to

perform time-slot interchange functions with different throughput delay capabili-

ties on the per-channel basis. For voice applications, variable throughput delay

is best as it ensures minimum delay between input and output data. In wideband

data applications, constant throughput delay is best as the frame integrity of the

information is maintained through the switch.

The delay through the device varies according to the type of throughput

delay selected in the V/C bit of the connection memory.

VARIABLE DELAY MODE (V/C BIT = 0)

In this mode, the delay is dependent only on the combination of source and

destination channels and is independent of input and output streams. The

minimum delay achievable in the IDT72V70800 is three time-slots. If the input

channel data is switched to the same output channel (channel n, frame p), it will

be output in the following frame (channel n, frame p+1). The same is true if input

channel n is switched to output channel n+1 or n+2. If the input channel n is

switched to output channel n+3, n+4,..., the new output data will appear in the

same frame. Table 1 shows the possible delays for the IDT72V70800 in the

variable delay mode.

CONSTANT DELAY MODE (V/C BIT = 1)

In this mode, frame integrity is maintained in all switching configurations by

making use of a multiple data memory buffer. Input channel data is written into

the data memory buffers during frame n will be read out during frame n+2. In

the IDT72V70800, the minimum throughput delay achievable in the constant

delay mode will be one frame. See Table 2 for possible delays in constant delay

mode.

MICROPROCESSOR INTERFACE

The IDT72V70800 provides a parallel microprocessor interface for multi-

plexed or non-multiplexed bus structures. This interface is compatible with

Motorola non-multiplexed and multiplexed buses.

If the IM pin is low a Motorola non-multiplexed bus should be connected to

the device. If the IM pin is high, the device monitors the AS/ALE and DS/RD to

determine what mode the IDT72V70800 should operate in.

If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed

timing is selected. If DS/RD is high at the rising edge of AS/ALE, then the mode

2 multiplexed bus timing is selected.

For multiplexed operation, the required signals are the 8-bit data and

address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch

enable (AS/ ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR),

Chip select (CS) and Data transfer acknowledge (DTA). See Figure 12 and

Figure 13 for multiplexed parallel microport timing.

For the Motorola non-multiplexed bus, the required signals are the 16-bit

data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines

(CS, DS, R/W and DTA). See Figure 14 and 15 for Motorola non-multiplexed

microport timing.

The IDT72V70800 microport provides access to the internal registers,

connection and data memories. All locations provide read/write access except

for the data memory and the frame alignment register which are read only.

MEMORY MAPPING

The address bus on the microprocessor interface selects the internal

registers and memories of the IDT72V70800.

If the A7 address input is low, then A6 through A0 are used to address the

interface mode selection (IMS), control (CR), frame alignment (FAR) and frame

input offset (FOR) registers (Table 4). If the A7 is high, then A6 through A0 are

used to select 128 locations corresponding to data rate of the ST-BUS

. The

address input lines and the stream address bits (STA) of the control register allow

access to the entire data and connection memories. The control and IMS

registers together control all the major functions of the device, see Figure 3.

As explained in the Serial Data Interface Timing and Switching Configura-

tions sections, after system power-up, the IMS register should be programmed

immediately to establish the desired switching configuration.

The data in the control register consists of the memory block programming

bit (MBP), the memory select bit (MS) and the stream address bits (STA). As

explained in the Memory Block Programming section, the MBP bit allows the

entire connection memory block to be programmed. The memory select bit is

COMMERCIAL TEMPERATURE RANGE

IDT72V70800 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 512 x 512

Connection Memory

10000001 10000010

Data Memory

0 0

1 0

1 1 3

Stream

Control Register

5709 drw03

10000000

The Control Register is only accessed when A7-A0

are all zeroed. When A7 =1, up to 128 bytes are

randomly accessable via A0-A6 at any one instant.

Of which stream these bytes (channels) are accessed

is determined by the state of CR

1 -CR

6CR

5CR

4CR

3CR

2CR

1CR

11111111 External Address Bits A7-A0

Channel 0 Channel 1 Channel 2

Channel 127

Figure 3. Addressing Internal Memories

used to designate the connection memory or the data Memory. The stream

address bits select internal memory subsections corresponding to input or output

serial streams.

The data in the IMS register consists of block programming bits (BPD0-

BPD4), block programming enable bit (BPE), output stand by bit (OSB) and start

frame evaluation bit (SFE). The block programming and the block programming

enable bits allows users to program the entire connection memory (see Memory

Block Programming section). If the ODE pin is low, the OSB bit enables (if high)

or disables (if low) all ST-BUS

output drivers. If the ODE pin is high, the contents

of the OSB bit is ignored and all TX output drivers are enabled.

CONNECTION MEMORY CONTROL

If the ODE pin or the OSB bit is high, the OE bit of each connection memory

location controls the output drivers-enables (if high) or disables (if low). See

Table 4 for detail.

The processor channel (PC) bit of the connection memory selects between

Processor Mode and Connection Mode. If high, the contents of the connection

memory are output on the TX streams. If low, the stream address bit (SAB) and

the channel address bit (CAB) of the connection memory defines the source

information (stream and channel) of the time-slot that will be switched to the output

from data memory.

The V/C (Variable/Constant Delay) bit in each connection memory location

allows the per-channel selection between variable and constant throughput

delay modes.

If the LPBK bit is high, the associated TX output channel data is internally

looped back to the RX input channel (i.e., RX n channel m data comes from the

TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For

proper per-channel loopback operation, the contents of the frame delay offset

registers must be set to zero.

INITIALIZATION OF THE IDT72V70800

After power up, the state of the connection memory is unknown. As such,

the outputs should be put in high impedance by holding the ODE low. While the

ODE is low, the microprocessor can initialize the device, program the active

paths, and disable unused outputs by programming the OE bit in connection

memory. Once the device is configured, the ODE pin (or OSB bit depending

on initialization) can be switched.

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