72V70800TFG Datasheet 72V70800PFG, 72V70800PFG8, 72V70800TFG | P7-P9

IDT72V70800 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 512 x 512

COMMERCIAL TEMPERATURE RANGE

TABLE 4 — OUTPUT HIGH IMPEDANCE CONTROL

TABLE 3 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING

TABLE 2 — CONSTANT THROUGHPUT

DELAY VALUE

TABLE 1 — VARIABLE THROUGHPUT

DELAY VALUE

NOTE:

1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.

Delay for Variable Throughput Delay Mode

Input Rate (m – output channel number)

(n – input channel number)

m < n m = n, n+1, n+2 m > n+2

8.192 Mb/s 128 – (n-m) time-slots m-n + 128 time-slots m-n time-slots

Delay for Constant Throughput Delay Mode

Input Rate (m – output channel number)

(n – input channel number)

8.192 Mb/s 128 + (128 – n) + m time-slots

(1)

A6 A5 A4 A3 A2 A1 A0 Location

00000000Control Register, CR

00000001Interface Mode Selection Register, IMS

00000010Frame Alignment Register, FAR

00000011Frame Input Offset Register, FOR

10000000Ch0

10000001Ch1

100......

10011110Ch30

10011111Ch31

10100000Ch32

10100001Ch33

101......

10111110Ch62

10111111Ch63

11000000Ch64

11000001Ch65

110......

11111110Ch126

11111111Ch127

OE bit in Connection ODE pin OSB bit in IMS TX Output Driver

Memory Register Status

0 Don’t Care Don’t Care Per Channel

High-Impedance

1 0 0 High-Impedance

1 0 1 Enable

1 1 1 Enable

1 1 0 Enable

COMMERCIAL TEMPERATURE RANGE

IDT72V70800 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 512 x 512

TABLE 5 — CONTROL REGISTER (CR) BITS

TABLE 6 — INTERFACE MODE SELECTION (IMS) REGISTER BITS

Read/Write Address: 00H,

Reset Value: 0000

1514131211109876543210

0000000000MBPMS00STA1 STA0

Bit Name Description

15-6 Unused Must be zero for normal operation.

5 MBP When 1, the connection memory block programming feature is ready for the programming of Connection

(Memory Block Program) Memory high bits, bit 11 to bit 15. When 0, this feature is disabled.

4 MS When 0, connection memory is selected for read or write operations. When 1, the data memory is selected

(Memory Select) for read operations and connection memory is selected for write operations.

(No microprocessor write operation is allowed for the data memory.)

3-2 Unused Must be zero for normal operation.

1-0 STA1-0 The binary value expressed by these bits refers to the input or output data stream, which corresponds

(Stream Address Bits) to the subsection of memory made accessible for subsequent operations. (STA1 = MSB, STA0 = LSB)

Read/Write Address: 01H,

Reset Value: 0000

Bit Name Description

15-10 Unused Must be zero for normal operation.

9-5 BPD4-0 These bits carry the value to be loaded into the connection memory block whenever the memory block

(Block Programming Data) programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is

set to 1, the contents of the bits BPD4-0 are loaded into bit 15 and 11 of the connection memory. Bit 10 to

bit 0 of the connection memory are set to 0.

4 BPE A zero to one transition of this bit enables the memory block programming function. The BPE and

(Begin Block Programming BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set

Enable) HIGH, the device requires two frames to complete the block programming. After the programming function

has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE

or MBP can be set to 0 to abort to ensure proper operation. When BPE = 1, the other bit in the IMS register

must not be changed for two frames to ensure proper operation.

3 OSB When ODE = 0 and OSB = 0, the output drivers of TX0 to TX3 are in high impedance mode. When

(Output Stand By) ODE= 0 and OSB = 1, the output driver of TX0 to TX3 function normally. When ODE = 1, TX0 to TX3

output drivers function normally.

2 SFE A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR

(Start Frame Evaluation) register changes from zero to one, the evaluation procedure stops. To start another fame evaluation

cycle, set this bit to zero for at least one frame.

1-0 Unused For normal operation, bit 1 = 1 and bit 0 = 0.

1514131211109876543210

000000BPD4 BPD3 BPD2 BPD1 BPD0 BPE OSB SFE 1 0

IDT72V70800 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 512 x 512

COMMERCIAL TEMPERATURE RANGE

0123 45678 910111213141516

ST-BUS

Frame

Offset Value

FE Input

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

GCI Frame

CLK

Offset Value

FE Input

(FD[10:0] = 06

)

(FD11 = 0, sample at CLK LOW phase)

(FD[10:0] = 09

)

(FD11 = 1, sample at CLK HIGH phase)

5709 drw04

CLK

TABLE 7 — FRAME ALIGNMENT REGISTER (FAR) BITS

Figure 4. Example for Frame Alignment Measurement

Bit Name Description

15-13 Unused Must be zero for normal operation.

12 CFE When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment

(Complete Frame Evaluation) offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0.

11 FD11 The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1)

(Frame Delay Bit 11) or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.

10-0 FD10-0 The binary value expressed in these bits refers to the measured input offset value. These bits are rest to

(Frame Delay Bits) zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)

Read/Write Address: 02

Reset Value: 0000

1514131211109876543210

0 0 0 CFE FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

72V70800TFG

Mfr. #:

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Manufacturer:

IDT

Description:

Digital Bus Switch ICs 3.3V 512X512 TIS SWITCH

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72V70800TFG

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